Question about Xilinx ISE IP Core Binary Counter

[williamd4112]

I have learned verilog for a while. But I almost work on basic components. This is the first time that I use IP core to generate some basic components.

I try the binary counter. Generate and instantiate successfully. But when I use my testbench to check its functionality, I got some strange problems.

This is my testbench:

module Counter_t(
    );
	reg clk;
	wire[15:0] q;
	
	Counter counter(
		.clk(clk), // input clk
		.q(q) // output [15 : 0] q
	);
	
	always #5 clk = ~clk;
	initial begin
		clk = 0;
		$monitor("%g:\t%b\n",$time,q);
	end
endmodule

If it work properly, it should count in 10 unit time.
But output in monitor is the following ...

0:	0000000000000000

105:	0000000000000001

115:	0000000000000010

125:	0000000000000011

135:	0000000000000100

Why ? Why it start after 100 unit time ? I have checked it data sheet, but I still have no idea.

 

[ads-ee]

I just tried it with Vivado 2014.3 and it correctly starts counting at a time unit of 5.

I then tried using ISE 14.7 and the counter starts up at 105 time units due to the following code in glbl.v:

---

Code Verilog - [expand]
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initial begin
    GSR_int = 1'b1;
    PRLD_int = 1'b1;
    #(ROC_WIDTH)
    GSR_int = 1'b0;
    PRLD_int = 1'b0;
    end

---

ROC_WIDTH is 100000 with a `timescale 1ps/1ps which delays the GSR_int deassertion by 100 ns.