Hi,
(Please don't be scared by my lengthy post, I just wat to explain my thinking)
I dont really mind if its TTL or CMOS, i Just wanted to make the point the signal needed to be releveled to work with the PFD.
To get stable output and to get a reliably running circuit you need to choose the right IC (and family) and keep on the ICs specifications.
Honestly it's hard for me to find out the input signal requirements in old CD4046 datasheet. Since we don't have the complete schematic I don't know which signal with which levels and waveform you feed to which IC and pin.
I'm probably wrong here: can the same op-amp be used as a comparator (assuming its fast enough of course)?
An Opamp is an Opamp, a comparator is a comparator, each desined for it's job. Sadly they use the same schematic symbol, but the function and requirements are different.
There are several threads here (and in the internet) discussing the difference.
In short:
* Opamp
analog input, analog output. Negative feedbacked. Differential input voltage should be almost zero to avoid input stage saturation, output voltage should never become saturated at the supply rails. Else they come out of regulation which causes extra delay, in worst case phase reversal.
* Comparator:
analog input, digital output. Not negative feedbacked, maybe positive feedbacked. No analog regulation loop. Differential input voltage may be big, input stage is designed not to get saturated. Output stage is desiged to go to the supply rails (no must). They generate output with fast edges. No phase reversal.
The VCO has a control voltage, vtune.
We live in different countries, have different languages, you have all the background knowledge about your application, we not.
When you use different names and terminology as in the datasheet, then maybe you get wrong response..
This control voltage is the issue. It is connected to both the BK 24V output and the output from the LPF (see pic below). We can remove the BK supply once the frequency difference between the 1.5 GHz reference and N/16 output is small enough to function within the amp and PFD bandwidth.
In your new block diagram the Vtune is connected to the both the 24V supply and the 5V voltage divider.
I assume this is optional connection...
If I understand correctly, then in case the VCO output frequency becomes too high and the PFC refuses to work. It can't lock
If so, then I see some options:
* use a faster PFC ( 74HC4046 is about 10 times faster than CD4046)
* ramp up Vtune slowly enough that the PLL safely can lock. This can be done by a slow RC, maybe with the help of diodes.
My idea: on power down the C gets discharged by a diode. On power up the C charges slowly ... limiting the Vtune voltage.
Then at some point (close to the desired VCO frequency) the LPF output takes over and the PLL should lock.
Klaus