Question about verilog syntax

Status
Not open for further replies.

adgjl40112

Newbie level 5
Joined
Mar 26, 2010
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,349
Question about verilog

Hi friends, I want to ask a question about verilog syntax;
I want to have a function for verilog which works like in c codes as following
int a = 1;
int b[10];
if (b[a] == 1) // what I want is use variable index

I don't know how can I fulfill this functionality.
Another question is when writing FSM.

If I have some if else statement, normally where should I place? In combinational part or sequential part. thx a lot
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…