In DPLL design, two frequency should be input: one is reference frequency, the other is the frequency to operate counter and inc_dec module, which is much higher, 8 times(or higher) of reference frequency. So in the USB design where the data rate is 12Mb/s or 1.5Mb/s, there is no problem. But if the reference frequency is much higher, then the timing of the design will be very ambitious. Can this problem be solved?
snakebites,
I don't think that exact problem is easy to solve. However, there is more than one way to skin the cat. What is the real problem you are trying to solve?