Question about Timing Constraints in ISE

[sameem_shabbir]

I have clock oscillator of 100MHz on my FPGA Board.

I have given timing constraints to clock (Max freq 100MHz) in my UCF file

Hower synthesis gives the max freq of 54MHz in Synthesis report

And I get the warning when Implement Design is running
One or more timimg constraints are not met

How should i make ISE abide by those constraints.

Or is it like this that the Max freq given in synthesis report doesnot matter.

 

[k_vlsi]

Re: Timing Constraints

Though you have given a constraint of 100 MHz, your design is probably not able to work at more than 54 MHz.
I am not sure about the settings in ISE to do timing optimization.
If you want the currently implemented design to work reliably on the FPGA, you will have to use a PLL or DCM to bring the oscillator frequency to about 50MHz and then use that to clock your design.

 

[banjo]

Timing Constraints

There are several settings in ISE where you can change the effort level in the design. This will make the FPGA build times much longer, but it gives it a better chance on making your timing requirements because it causes the tools to try harder. If that does not work, then you need to review the signals that are not making timing and either re-write the logic to be faster, or relax the timing constraints on those nets.
How do you make the logic faster? The primary way is to add pipelining stages. These are flip-flops that break large combinatorial sections in to smaller chunks that the place and route with less prop delay.
Why would you relax timing constraints? Because some signals will not change on every 100MHZ clock edge. If a signal is coming from an external source which updates only every three or four 100MHZ clocks, then the signal cannot propagate through the FPGA any faster than that. The ISE tool has no way of knowing the speed of the external signals and therefore assumes the 100MHZ worst case. The way you tell ISE about this is by placing specific relaxed timing constraints on those signals.

 

[cherjier]

Timing Constraints

i always check my synthesis timing report, if ur timing is close to the target frequency, than the PAR might able to optimise it but not recommanded. if the timing is off with a big gap, most of the time the PAR will fail to meet your timing.

you might also analyze your STA report to look for the critical path, redesign the path or break the path by adding register in between. sometimes solving 1 critical path might improve your timing alot.

just my experience.... peace

 

[raka200]

Re: Timing Constraints

Hello,
100MHz is quite a low frequency for virtex2 pro, you should check the way you have written your code.
You should avoid huge asynchronous computation between register latch, use process instead...
You should also flop several times your high frequency signals, it will ease the PAR job...

good luck