If you are using the transmission gate the delay is determined by the current of transistors which drive your transmission gate. For proper sizing, it is better considering the current that will pass through your transmission gate.
It is better to use the same pmos/nmos ratio as other cmos gates for layout but you can iterate sizes for best delay.
Your sizing will also affect the clock feed-through to your output. For proper design I strongly recommend you to go through Chapter 4 (Section 4.1) of "CMOS Analog Circuit Design" from Allen and Holberg.