LAORUAN
Newbie level 5
hello, every one.
My question is as follow：
I think I have constraint the output clock, but why does Timequest still remind that the output ports is not constraited.
Thank you!
My question is as follow：
Code:
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {iCLK} -period 20.000 -waveform { 0.000 10.000 } [get_ports {iCLK}]
create_clock -name {CLK_Virtual} -period 20.000 -waveform { 0.000 10.000 }
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {CLK_50M_180} \
-source [get_pins {DDS_u0|PLL_50M_u0|altpll_component|auto_generated|pll1|inclk[0]}]
-phase 270.000 [get_pins {DDS_u0|PLL_50M_u0|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {DAC_Output_clk}
-source [get_pins {DDS_u0|PLL_50M_u0|altpll_component|auto_generated|pll1|clk[0]}] \
[get_ports {oDAC_CLK}]I think I have constraint the output clock, but why does Timequest still remind that the output ports is not constraited.
Thank you!