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Question about spi slave on fpga....

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Sink0

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I am writing a code for a spi slave on verilog for FPGA, but i have a question about how the SPI should behave. Should the Slave Select pin reset the SPI shift register counter, or just disable it? I mean.. if for some reason the SPI clock do no trigger my Flip-Flop (ok thats almost impossible), the counter is going to be on a wrong position. If i reset it with the Slave Select it can get back to the right one.. so should it reset or not?

Thank you!
 

thirugnanam.ram

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Can you tell me the partname of the serial ADC chip? If you disable the Slave select/Chip select the slave will reset the internal shift register counter.
 

Sink0

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No nmno.. there is no ADC.. the FPGA is the Slave... but anyway.. thats al i need..
 

yadog

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you should design your module refer to the timing graph from the Master SPI device
 

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