Full Member level 6
I am writing a code for a spi slave on verilog for FPGA, but i have a question about how the SPI should behave. Should the Slave Select pin reset the SPI shift register counter, or just disable it? I mean.. if for some reason the SPI clock do no trigger my Flip-Flop (ok thats almost impossible), the counter is going to be on a wrong position. If i reset it with the Slave Select it can get back to the right one.. so should it reset or not?