I just to ask if my shift register code below is correct because the output that we get lacks one more shift..
example:
we need a data that looks like this 11111111 but the output we get is 01111111
Code:
begin
if (clk'event and clk = '1') then
if (TDRE = '1') then
dr <=iempty;
dr <= Din;
end if;
if (RDRF ='1') then
dr<=sr;
Dout <= dr;
end if;
if (load = '1') then
sr <= dr;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rcve); --last rcved bit :research
end if;
end if;
its difficult to understand what you're talking about out of context. Theres nothing wrong with your code, and the problems you are having could happen for all sorts of reasons to do with inputs. I suspect its the inputs thats wrong, not the code.
its difficult to understand what you're talking about out of context. Theres nothing wrong with your code, and the problems you are having could happen for all sorts of reasons to do with inputs. I suspect its the inputs thats wrong, not the code.
yeah unfortunately the part where we get the 01111111 (the read command) can't be tested on a test bench, i guess, because the one responsible on giving data is the other device. It's the one pulling down the signal (pulled-up signal) that would be received by the shift register. We did test the write command though and it did work in the test bench and on the fpga.
no.. i forgot to remove dr<= iempty lol my mistake. its just something to test the dr signal.
so you mean to say that it's better if I just make it Dout <= sr.. hmm do you have any suggestions on how i could make the data register because it seems like its delaying the signal and it might be a reason why the output is not shifted properly.
I assume that this code is inside a process, note that dr, sr are signals so
Code VHDL - [expand]
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dr<=sr;-- the sr value will be assigned the next time that the process in entered, dr will keep the same value it had when the process was entered
Dout <= dr;-- that means that in this line you assign the "old" dr endif;
I assume that this code is inside a process, note that dr, sr are signals so
Code VHDL - [expand]
1
2
3
dr<=sr;-- the sr value will be assigned the next time that the process in entered, dr will keep the same value it had when the process was entered
Dout <= dr;-- that means that in this line you assign the "old" dr endif;