Question about shift register (VHDL)

[mjvm171]

Hello

I just to ask if my shift register code below is correct because the output that we get lacks one more shift..
example:

we need a data that looks like this 11111111 but the output we get is 01111111

begin
if (clk'event and clk = '1') then
if (TDRE = '1') then
dr <=iempty; 
dr <= Din;
end if;

if (RDRF ='1') then
dr<=sr;
Dout <= dr;
end if;

if (load = '1') then
sr <= dr;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rcve); --last rcved bit :research

end if;
end if;

Assistance is really appreciated

Thank you:grin:

 

[TrickyDicky]

sr looks like a shift register to me, using dr to load.

 

[mjvm171]

sr looks like a shift register to me, using dr to load.

yeah.. it's supposed to be a loading and unloading signal. Is that wrong? Should i just turn it to a buffer or something?

umm but anyways i did try to unload the contents of sr directly to Dout (Dout<=sr) but we still got 01111111 instead of 11111111...


I am really confused as to why this is happening..

 

[TrickyDicky]

its difficult to understand what you're talking about out of context. Theres nothing wrong with your code, and the problems you are having could happen for all sorts of reasons to do with inputs. I suspect its the inputs thats wrong, not the code.

 

[mjvm171]

its difficult to understand what you're talking about out of context. Theres nothing wrong with your code, and the problems you are having could happen for all sorts of reasons to do with inputs. I suspect its the inputs thats wrong, not the code.

hmm i see.. well then i'll have to check that but my input here is actually a data read from another device..

Nevertheless, Thanks for your answer.

 

[TrickyDicky]

have you testbenched this code?

 

[mjvm171]

have you testbenched this code?

yeah unfortunately the part where we get the 01111111 (the read command) can't be tested on a test bench, i guess, because the one responsible on giving data is the other device. It's the one pulling down the signal (pulled-up signal) that would be received by the shift register. We did test the write command though and it did work in the test bench and on the fpga.

 

[FvM]

Without knowing the input and expected output signal waveforms, nothing can be said.

I wonder, why the output is delayed by an additional clock cycle?

if (RDRF ='1') then
dr<=sr;
Dout <= dr;
end if;

 

[mjvm171]

Without knowing the input and expected output signal waveforms, nothing can be said.

I wonder, why the output is delayed by an additional clock cycle?

if (RDRF ='1') then
dr<=sr;
Dout <= dr;
end if;

is the additional clock cycle dr<=sr; ?

its supposed to be the data register. Hmm.. I'm kind of new in VHDL so I get lost most of the times ending with me not knowing what to do.

 

[alexan_e]

Also this part

if (clk'event and clk = '1') then
if (TDRE = '1') then
dr <=iempty;
dr <= Din;
end if;

dr will be assigned the value you wrote last which means that dr <=iempty; will be ignored.
Was one of the lines supposed to be sr and not dr?

Alex

 

[mjvm171]

Also this part

if (clk'event and clk = '1') then
if (TDRE = '1') then
dr <=iempty;
dr <= Din;
end if;

dr will be assigned the value you wrote last which means that dr <=iempty; will be ignored.
Was one of the lines supposed to be sr and not dr?

Alex

no.. i forgot to remove dr<= iempty lol my mistake. its just something to test the dr signal.

so you mean to say that it's better if I just make it Dout <= sr.. hmm do you have any suggestions on how i could make the data register because it seems like its delaying the signal and it might be a reason why the output is not shifted properly.

thank you

 

[alexan_e]

I assume that this code is inside a process, note that dr, sr are signals so

---

Code VHDL - [expand]
1
2
3
dr<=sr;  -- the sr value will be assigned the next time that the process in entered, dr will keep the same value it had when the process was entered
Dout <= dr;     -- that means that in this line you assign the "old" dr 
end if;

---

Alex

 

[mjvm171]

I assume that this code is inside a process, note that dr, sr are signals so

---

Code VHDL - [expand]
1
2
3
dr<=sr;  -- the sr value will be assigned the next time that the process in entered, dr will keep the same value it had when the process was entered
Dout <= dr;     -- that means that in this line you assign the "old" dr 
end if;

---

Alex

oh I see, I could now understand better thank you very much..