lovseed said:I am designing a 14-bit 50M current-steering DAC.
And the SFDR is only about 62dB for 23.4375M data and 50M sampling frequency.
Any good paper working on this?
rajanarender_suram said:Try to reduce the glitch(which can be done by small modifications in the current-cells), because higher the glitch longer the settling time.
Added after 4 minutes:
lovseed said:I am designing a 14-bit 50M current-steering DAC.
And the SFDR is only about 62dB for 23.4375M data and 50M sampling frequency.
Any good paper working on this?
U r working with 50M clock for 23.4375M data which is near nyquit rate... its quite obvious that u get poor SFDR
jerryzhao said:Could you tell me the DAC's power supply and output swing?
The simulation result is right? Why the 5nH inductor's SFDR is better than others.
I think if you use the cascode, the PSRR will not very bad. And the noise is not main cause for bad SFDR( if noise very large is the main cause).
I think when you output swing change, the Vds of current MOS will small change. that will let DAC's INL bad. If you are not compensation that will lead a large harmonic distortion.
U should care it.
gdhp said:"(2)Since the sampling clock is 50M (20ns), I am getting the 18ns result from each cycle to do FFT.Which means that i take the settling time to be 18ns( I think the final result should not worse than 18ns ). "
hi lovseed
when you do fft in hspice, how you can verify the point you get is the
settled point?
what is the meaning for "I am getting the 18ns result from each cycle to do FFT"?
jerryzhao said:Hi lovseed:
Are your current cell always on? If the current cell always on, you put the output switch to out or out_. I think it will settle quickly. I think 18ns for settling time is enough. If DAC's output don't settle, I think u should check your current cell circuit and timing circuit.
Be care for the switch's timing and switch's size.
The size too small, it slow.but too large the clock feed-through is large.
Never shut down current in your current cell. otherwise it will not settle.
About compensation:
I add some current cell.I don't find some paper about it.
Only in my design, I add some current cell. When the output large I add a current cell to output especially the LSM block shift to MSB block.
jerryzhao said:1 When the power supply is ideal, make DA's settleing time < 15ns. I think u have done it.
2 Make the glitch as small as possible.
3 When simulate dirty power supply. please conect the two couple capacitor one 10uf another 0.1uf (PCB applaction connceted) then connect inductor with power.
4 If the digital power connect with analog power, Please use 1~2ohm's resistor connect D_power and A_power to main Power.
5 The main power, D_power(digital power), A_power all use couple capacitors.(the power on PCB connect like that)
Don't worry about it. I think everything will be ok.
jerryzhao said:1 Confirm current cell and cascode transistor always are saturated.
2 The next time you design current mirror, I don't think need use such accurate size of mos transistor.
3 The couple capacitor is on PC board, they are 10uF and 0.1uF, they are parallel.
4 When u give the DC step digital input, the most large glitch as small as posbile.
5 If you loading resistor is large. u can pallel a resistor in order to increase current, then decrease the settling time. (loading may be 75 ohm, you can parallel a resistor on PCB borad)
6 Ur W*L so large, so the die size is very large. I don't think it is good for mismatch.
7 Ur Engish is better than me.
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