Deserializer
In fact I am designing a serdes in VHDL for ASIC's IPs Interconnect.
The serializer drived by the clock 1 generates the serialised data from a parallel data.
The deserializer utilises the incoming data to generate the clock 2 (independent from the seralizer's one) whch is used to synchronize the circuitry of the deserializer.
I thing that this is clear.
Added after 13 minutes:
@Master_Picengineer
If you are designing transcievers as SERDES, In order to generate the clock you have to send at the beginning a serie of '1' and '0' after that you sent the data. This enable to know the simpling rate of the data.
I am searching for material on this issue.
@ all,
please if anybody have docs upload it.
Regards,
Mouzid