hrkhari
Full Member level 4
Hi Guys:
With reference to the attached pMOS VCO topology, it is stated that the pMOS implementation enables low power supply operation and high tuning range. Respective to the latter advantage it is also stated that:
“The overdrive (Vgs-Vt) voltage of pMOS transistors is 0.5V, resulting in an output DC level of 0.55V (see Figure) at 1.8V of supply. This means that the tuning voltage can go down to 0V and up to 1.8V without forward biasing the P/N diodes”
I don’t see how the DC level of 0.55V is obtained from the circuit attached, can anyone guide me in explaining the mathematical logic behind this?. Thanks in advance.
Rgds
With reference to the attached pMOS VCO topology, it is stated that the pMOS implementation enables low power supply operation and high tuning range. Respective to the latter advantage it is also stated that:
“The overdrive (Vgs-Vt) voltage of pMOS transistors is 0.5V, resulting in an output DC level of 0.55V (see Figure) at 1.8V of supply. This means that the tuning voltage can go down to 0V and up to 1.8V without forward biasing the P/N diodes”
I don’t see how the DC level of 0.55V is obtained from the circuit attached, can anyone guide me in explaining the mathematical logic behind this?. Thanks in advance.
Rgds