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Question about PLL frequency in at-speed test for DFT

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liwei039

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when I do at-speed DFT, I want to using the PLL output as refclk1 for launch and capture clock.
But there is a question, if the default PLL output clock frequency is not what I want. How can I make the PLL output clock turn to the right frequecy?
Use strap pin?

2. Can I config the PLL register to change the PLL frequency? I dont think so, but why?

thanks
 

maulin sheth

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Hello

If you need to generate required PLL frequency..thn you need to config the PLL register.Because only through PLL we can generate at speed frequency.
 

liwei039

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So, I can config the PLL register when the chip is under the scan mode. the frequency of PLL config register ck pin is scan clock?
 

maulin sheth

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Yes,you can do it.
OCC is on your chip or not? Basically through OCC we generate the clock (scan,launch and capture clocks).
 

liwei039

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Thanks, yes, there is OCC in my chip. Is there some other things to be done besides configuration PLL registers?
Due to the PLL needs some time to be stable after configuration, so what I should do in the ATPG patterns? waiting some cycle times ?
 

maulin sheth

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For that you need the documentation of PLL which is used in your design. yea we have to give some time to stable the required PLL output....yea..you have to wait for some cycles...
 

liwei039

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Thanks a lot. Can I use the strap pin for configuration the PLL? Is this a little fast than RISC to config that PLL register?
 

maulin sheth

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I think whn you config the PLL thn the PLL ip is in functional mode, thn by using the PLL lock and power down mode, you can switch to test mode (this information you can get from the PLL documentation)...
Yea if any strap pin is available thn we can use it....

BTW you can refer the testbench of PLL for just understanding how to work with PLL for particular frequency...
 

liwei039

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Thank you very much. Do you have a simple testbench and PLL design or PLL documentation.

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Thank you very much. Do you have a simple testbench and PLL design or PLL documentation.
 

maulin sheth

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Sorry.I am DFT engineer so I don't have the simple PLL testbench.
Really sorry I can't help for document and testbench.
 

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