Question about performance of cache in AT91RM9200

[coros]

Hi everybody,

I'm doing image processing project on the AT91RM9200, so I want to increase performance by enabling the cache and the MMU. Here is the code:

void init_TLB() {
uint i, j, a; uint *tlb = (uint*)0x20000000;
for (i=0; i<4096; ++i) {
tlb = 0x12 | (i << 20);
}
for (i=512; i<528; ++i) {
tlb |= 0xC; // enable write_back cache for SDRAM
}
i = 0x20000000;
asm ("mcr p15, 0, %0, c2, c2, 0" : : "r"(i)); // set TLB base
i = 3;
asm ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i)); // set domain access
i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0" : : "r"(i)); // invalidate ICache & DCache
i = 0xC000107D;
asm ("mcr p15, 0, %0, c1, c0, 0" : : "r"(i)); // enable MMU & ICache & DCache & asyn clock
}

Then I measure the performance by counting the number of svd decompositions of a 6x6 matrix in 2.5s.

a = AT91C_BASE_ST->ST_CRTR + 5;
i = 0;
while (a > AT91C_BASE_ST->ST_CRTR) {
Q = V;
svd(Q, W, E);
++i;
}
std::cout << "\nsvd of Q\n" << W << "\nCalculated " << i << " times in 2.5s";

I get following results:
no cache 33 times
only instruction cache 270
data and instruction cache 35

Why is it so slow when both caches are enabled? It so slow as with no cache.
Thanks