Question about inserting an 10x10 array in vhdl

[triggerman]

Question about an array

I would like to insert an 10x10 array in vhdl.Each element of this array would be a bit vector of 8 bits.So i declare a new type of an 10x10 array and a signal to refer to this array.The problem is that if i declare an input of this type of array the system will use too many pins and this is not practical.It will use 800 pins.So i want to insert the values to each row of the array every rising edge of a clock.For this purpose i declare a signal which will have 10 cells(1x10) in order to put the values of this signal to the first row of the array,the next rising edge to put the values of this signal to the second row of the array etc...The problem is how can i refresh every time the values of this signal in order to put different values in every row of the array and not the same.Here is what i did:

PACKAGE newtype IS
TYPE vector_array IS ARRAY (1 TO 10,1 TO 10) OF BIT_VECTOR(7 DOWNTO 0);
SIGNAL sig : vector_array;
TYPE vector_array1 IS ARRAY (1 TO 10) OF BIT_VECTOR(7 DOWNTO 0);
SIGNAL sig1 : vector_array1;
END newtype;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.newtype.ALL;

ENTITY test IS
PORT ( clk : in std_logic;
input : in vector_array1);
END test;
ARCHITECTURE arch OF test IS
BEGIN
PROCESS(clk)
VARIABLE load : integer range 0 to 10;
VARIABLE j : integer range 1 to 10;
BEGIN
IF(clk'EVENT AND clk='1') THEN
load:=load+1;
IF(load<10) THEN
FOR j in 1 to 10 LOOP
sig1(j)<=input(j);
sig(load,j)<=sig1(j);
END LOOP;
END IF;
END IF;
END PROCESS;
END arch;

 

[farhada]

If this array is used internally, then you do not use any PINS, but they will be internal signals, so you should stick with the 10x10x8 declaration.

 

[triggerman]

So this code i wrote is correct?Does what is supposed to do?Thanks