nelly1
Junior Member level 3
Here is a topology presented by Sean R.Bradburn.
For high-side gate driver, when the switches are off, source voltage of Mp2 will fall to VDD. C1 discharges through diode.
But !!!!!!!!
why the gate voltage of Mp2 will fall further below its source voltage through diode???
Someone please help!!!!!!!!!!!!
For high-side gate driver, when the switches are off, source voltage of Mp2 will fall to VDD. C1 discharges through diode.
But !!!!!!!!
why the gate voltage of Mp2 will fall further below its source voltage through diode???
Someone please help!!!!!!!!!!!!