Aug 29, 2014 #1 N nervecell_23 Member level 1 Joined Apr 26, 2013 Messages 38 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,565 For instance, to implement an registered 2-bits 5:1 MUX: 1) use 'case' statement: Code: reg [1:0] out; wire [1:0] i_1, i_2, ... , i_5; always@(posedge clk) begin case(sel) 3'b000: out <= i_1; 3'b001: out <= i_2; ... endcase end I wonder whether the following 'array' style implementation would work or not: Code: wire [1:0] in [0:4]; wire [1:0] i_1, i_2, ... , i_5; reg [1:0] out; assign in[0] = i_1; assign in[1] = i_2; ... assign in[4] = i_5; always@(posedge clk) begin out <= in[sel]; end
For instance, to implement an registered 2-bits 5:1 MUX: 1) use 'case' statement: Code: reg [1:0] out; wire [1:0] i_1, i_2, ... , i_5; always@(posedge clk) begin case(sel) 3'b000: out <= i_1; 3'b001: out <= i_2; ... endcase end I wonder whether the following 'array' style implementation would work or not: Code: wire [1:0] in [0:4]; wire [1:0] i_1, i_2, ... , i_5; reg [1:0] out; assign in[0] = i_1; assign in[1] = i_2; ... assign in[4] = i_5; always@(posedge clk) begin out <= in[sel]; end
Aug 29, 2014 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 Yes, an array works, but will result in out of range and indeterminate results if the sel exceeds the range of the [0:4] index. I'm pretty sure anything outside the range become don't cares, but verify that is the behavior in your synthesis tool. Regards
Yes, an array works, but will result in out of range and indeterminate results if the sel exceeds the range of the [0:4] index. I'm pretty sure anything outside the range become don't cares, but verify that is the behavior in your synthesis tool. Regards