Question about different ways of describing MUX in Verilog

[nervecell_23]

For instance, to implement an registered 2-bits 5:1 MUX:

1) use 'case' statement:

reg [1:0] out;
wire [1:0] i_1, i_2, ... , i_5;

always@(posedge clk)
begin
    case(sel)
        3'b000: out <= i_1;
        3'b001: out <= i_2;
        ...
    endcase
end

I wonder whether the following 'array' style implementation would work or not:

wire [1:0] in [0:4];
wire [1:0] i_1, i_2, ... , i_5;
reg [1:0] out;

assign in[0] = i_1;
assign in[1] = i_2;
...
assign in[4] = i_5;

always@(posedge clk)
begin
    out <= in[sel];
end

 

[ads-ee]

Yes, an array works, but will result in out of range and indeterminate results if the sel exceeds the range of the [0:4] index. I'm pretty sure anything outside the range become don't cares, but verify that is the behavior in your synthesis tool.

Regards