hi all,
i'm trying to design a high precision current mirror /sink ,the current sank by each channel is up to 150mA and the error is less than 5% while the vds is only 1.0~2.0v.
i don't know if it 's possible to meet such requirement in cmos ? woule u give me some adversise?
for such a high current, i think not much you can play with other than increasing the W/L ratio. for the 5% variation, if you are talking about one current sink, u can always trim it to whatever you desire. but if you are talking about matching a bunch of these guys, you need to bias vgs >> vth for better matching which means smaller devices and large headroom.
for such a high current, i think not much you can play with other than increasing the W/L ratio. for the 5% variation, if you are talking about one current sink, u can always trim it to whatever you desire. but if you are talking about matching a bunch of these guys, you need to bias vgs >> vth for better matching which means smaller devices and large headroom.
for such a high current, i think not much you can play with other than increasing the W/L ratio. for the 5% variation, if you are talking about one current sink, u can always trim it to whatever you desire. but if you are talking about matching a bunch of these guys, you need to bias vgs >> vth for better matching which means smaller devices and large headroom.
Now you have 24 channel, each pass 150mA current with vds at least 1.0v . In other words, your chip will consume power of 24*150mA*1.0V=3.6W! Maybe you have to worry about the package first if your chip will go mass production.