Question about conversion direction

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taoshen

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conversion question

I think that
vhdl ------------------ verilog

variable -----------------> reg

signal ------------------> wire

process -------------------> always

May I be right?
 

Re: conversion question

Yes u are right!
I will add following!

vhdl -------> verilog
signal ----> wire if you are doing port mapping OR using signal outside process
signal ----> reg if you are assigning signal inside process block
 

Re: conversion question

nand_gates :

signal ----> wire if you are doing port mapping OR using signal outside process

=================================
Are you meanings that the "wire" denotes the signal that can communicate among
processes in one entity ?
 

Re: conversion question

No.. here is example of what i mean.....

VHDL code
signal a,b,c : std_logic;

u1: xyz_gate port map (a, b, c);

u2: pqr_gate port map (a, b, c);



Translates in Verilog

wire a,b,c;

xyz_gate u1(a, b, c);

pqr_gate u2(a, b, c);
 

Re: conversion question

Can you give me a example that "OR using signal outside process " ?
 

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