Question about a DAC in veriloga

[emont89]

I've created a DAC using veriloga(the code is below). My question is which function can I use in veriloga (in digital verilog the function posedge is used) to save the V(out) value only at the rising edge of the control signal?


module DAC_verilog(ctrl,b0,b1,b2,b3,b4,out);

input b0,b1,b2,b3,b4,ctrl;
output out;
voltage ctrl,b0,b1,b2,b3,b4,out;

parameter real vmin = -1.2 ;
parameter real vmax = 1.2 ;
integer ii;
parameter integer num_of_bits = 5;
integer bit[4:0];
real num;
integer control;

analog begin

control = V(ctrl);
bit[0] = V(b0);
bit[1] = V(b1);
bit[2] = V(b2);
bit[3] = V(b3);
bit[4] = V(b4);
num = 0;

if(control == 1) begin
for ( ii = 0 ; ii < num_of_bits ; ii = ii +1 ) begin
if(bit[ii] == 1) begin
num = num+(pow(2,ii));
end // end if
end // end for
end //end if

V(out) <+ num;

end // end analog

endmodule