In the snapshot u have provided there is no wire at all.
all the variables declared are reg.
when thinking of synthesis,
a wire is just a connection between two variables or signals.
say a clock signal. there is one clock port and u have to connect clock signal to all the registers. so u need a wire to connect all the registers.
so a wire cannot save or store a signal. its just a wire to connect the signals, and its not dependent on any signal. whatever comes to that wire its going to transfer.
But reg can stores a value and its fully dependent on clock and data. in the example in the snapshot he has written a code for shift register. what he is trying to explain is the dfference between bocking and non blobking statement.
if u simulate the design in modelsim,u will get the correct output but not in the case of synthesis. bcoz modelsim knows that it is a for loop and it has its own internal registers to store its intermediate varaibles, but synthesis tool will consider this as process which has to be completed in one single clock and it will assign assign the values all in one shot since there is no register to store the intermediate value.