pratibha m d
Junior Member level 3
Hi All,
Can anyone suggest me about the expectations of an interviewer from a candidate having 2yrs of experience in frontend VLSI design. I have exp in VHDL and Verilog.
I want to work in verification. What are the areas in which I have to update my knowlege.
Plz help me.
Rgds
Can anyone suggest me about the expectations of an interviewer from a candidate having 2yrs of experience in frontend VLSI design. I have exp in VHDL and Verilog.
I want to work in verification. What are the areas in which I have to update my knowlege.
Plz help me.
Rgds
