Querry on Pattern Simulation

[karthik_hr]

Hi,

I am new to pattern simulation. I have inserted the scan chain for a design with RTL compiler and generated patterns through Encounter test.
Now that I have generated the patterns, I am validating through ncsim and viewing the waveforms through simvision.
Since I am working on a small design which contains about 520 flops. I am not getting any sort of errors in prelayout simulation of patterns.
All the 2 lac odd patterns generated are passing without any miscompares.
I would like to know, what are the possible issues coming up while running prelayout pattern simulation?
Is it possible to force a miscompare in pattern simulation? If yes, how?

Thank you in advance.

 

[maulin sheth]

There is not any specific list which contain the issues of pre layout pattern simulation...It can be understood by experience only...
Yea we can force the logic value in the design but that is not the solution..we are forcing just to make sure that whatever we debug, it is correct or not.