Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Warning (20028): Parallel compilation is not licensed and has been disabled Warning (10034): Output port "D0" at test.v(36) has no driver Warning (10034): Output port "D1" at test.v(37) has no driver Warning (10034): Output port "D2" at test.v(38) has no driver Warning (10034): Output port "D3" at test.v(39) has no driver Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "D0" is stuck at GND Warning (13410): Pin "D1" is stuck at GND Warning (13410): Pin "D2" is stuck at GND Warning (13410): Pin "D3" is stuck at GND Warning (21074): Design contains 5 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "CLK" Warning (15610): No output dependent on input pin "CLR" Warning (15610): No output dependent on input pin "DATA" Warning (15610): No output dependent on input pin "LATCH" Warning (15610): No output dependent on input pin "SEL" Warning (20028): Parallel compilation is not licensed and has been disabled Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (169140): Reserve pin assignment ignored because of existing pin with name "CLK" Warning (169140): Reserve pin assignment ignored because of existing pin with name "CLR" Warning (169140): Reserve pin assignment ignored because of existing pin with name "D0" Warning (169140): Reserve pin assignment ignored because of existing pin with name "D1" Warning (169140): Reserve pin assignment ignored because of existing pin with name "D2" Warning (169140): Reserve pin assignment ignored because of existing pin with name "D3" Warning (169140): Reserve pin assignment ignored because of existing pin with name "DATA" Warning (169140): Reserve pin assignment ignored because of existing pin with name "LATCH" Warning (169140): Reserve pin assignment ignored because of existing pin with name "SEL"
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module test ( // {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE! CLK, CLR, D0, D1, D2, D3, DATA, LATCH, SEL // {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE! ); // {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE! input CLK; input CLR; output D0; output D1; output D2; output D3; input DATA; input LATCH; input SEL; // {ALTERA_IO_END} DO NOT REMOVE THIS LINE! // {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE! // {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE! endmodule
Any suggestions or procedure would be great.
I have a circuit as shown on the third post of this thread. For some reason the inputs and outputs are registered but not the muxes registers and counters.
I'm using the Lite version of the software.
Not sure what else to do.
Maybe this is a bug
well your counter's clock input is connected to CLR and not a clock that input is also connected to the GN pin of two of the muxes. The muxes themselves don't have clocks. The select is also screwy in this design as the final mux only selects the A inputs as it has a hard ground symbol attached to it.
I'm wondering how much digital design experience you have. I presume not too much given the state of this design. I'm not even sure of the intent of this design as the counter does nothing (the outputs aren't even attached to anything).
Don't get why you would use a counter as the LSB is only equivalent to a toggle FF. Most of the "counter" will be removed from the design as it's not used...leaving a toggle FF.
FYI, we can only go by what you post, and then have to guess the rest.Not the full circuit so I may be using the rest of the counter.
wow now this is plan rude. Originally I was unsure of your level of expertise. I was thinking you might be a junior engineer, hence my comment about the design, as it appears to be random connections with no decrenable function. It was also 'broken' I.e. drawn wrong. So am I expected to know that was an unintentional mistake on your part? Based on this comment I suppose you expect an expert to know exactly what you left out with no context?Sorry you could not understand it.
Maybe you over estimate what you know.
FYI, we can only go by what you post, and then have to guess the rest.
wow now this is plan rude. Originally I was unsure of your level of expertise. I was thinking you might be a junior engineer, hence my comment about the design, as it appears to be random connections with no decrenable function. It was also 'broken' I.e. drawn wrong. So am I expected to know that was an unintentional mistake on your part? Based on this comment I suppose you expect an expert to know exactly what you left out with no context?
Besides I'm not drawing schematics, I code this stuff in VHDL or Verilog and have worked on a number of first pass success ASIC designs, in architecture design, coding, and verification. So yes I do know my stuff.
So what you are saying is real designers don't do schematic design anymore? Shocking. What year is this, 1979? What is this VHDL you speak of?
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