shaiko
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I wrote the following VHDL function to determine the clock period in nanoseconds of a certain frequency.
In my entity I have an input defined as follows:
I apply the function "period_ns" on "frequency_x" as follows:
Note: the input "frequency_x" is driven by a constant and explicit value at the top entity.
When I synthesize my code. Quartus, gives the following errors:
As I mentioned - although "frequency_x" is defined as an unsigned input - it is driven by an explicit value from the top entity. So I really don't see why synthesis fails.
Code:
function period_ns ( frequency_hz : unsigned ) return unsigned is
variable second : unsigned ( 31 downto 0 ) := "00111011100110101100101000000000" ; -- 1,000,000,000 ns ( or 1 second )
variable result : unsigned ( 31 downto 0 ) ;
begin
result := restoring_divide ( second , resize ( frequency_hz , 32 ) ) ; -- restoring divide is another function I wrote in my package
return result ;
end function period_ns ;
Code:
frequency_x : in unsigned ( frequency_x_width - 1 downto 0 ) ; -- "frequency_x_width" is an entity generic
Code:
constant period_ns_frequency_x ( frequency_x ' range ) := period_ns ( frequency_x ) ;
When I synthesize my code. Quartus, gives the following errors:
Error (10346): VHDL error at package_functions.vhd(368): formal port or parameter "frequency_hz" must have actual or default value
Error (10657): VHDL Subprogram error at top.vhd(118): failed to elaborate call to subprogram "period_ns"
As I mentioned - although "frequency_x" is defined as an unsigned input - it is driven by an explicit value from the top entity. So I really don't see why synthesis fails.