PWM Generator and Control

[Ogbachi]

All,

I am working on 2-phase interleaved bidirectional dc-dc converter as shown in the circuit below. I have not been able to find answers to the following questions running through my mind. The questions are:

1. How do I generate two independent PWMs of 180 degrees out of phase with dead time? In this case considering 50 kHz switching frequency and 50% duty cycle.

2. Which PWM generator can suite my specifications-PIC microcontroller, IC or 555 timers? I have PIC16F88 in the lab, can it do the job?

3. What is the best switching technique I can use for my design? I am using IR2101 as my gate driver.

Mate, please assist me on this; I am new on converter design.

Many thanks,
Ibrahim.View attachment Power Circuit.zip

 

[mtwieg]

First of all, if you are using interleaved phases then you must use a current mode control scheme, meaning you do not actually generate PWM with variable duty cycle, but rather you just provide a clock, and the current control loop will settle on a duty cycle based on the peak current setpoint. So you only need to create phase interleaved clocks (not interleaved PWM). This can be done different ways depending on how many phases there are. Generally you use a combination of a ripple counter or johnson counter with some logic gates. There are also special ICs that are specialized for making phase interleaved clocks (look up LTC6902 and LTC6909).

Second, you're going to run into a lot of trouble if you actually try to build this circuit... those FETs are going to pop in seconds. At 50KHz you could get maybe 50A through them reliably. And you have 4V of headroom on Vds, so even under light load they're fail due to avalanche eventually. You should choose some FETs rated at 150V or more and use more phases (four at least), and possibly reduce your switching frequency.

 

[Ogbachi]

First of all, if you are using interleaved phases then you must use a current mode control scheme, meaning you do not actually generate PWM with variable duty cycle, but rather you just provide a clock, and the current control loop will settle on a duty cycle based on the peak current setpoint. So you only need to create phase interleaved clocks (not interleaved PWM). This can be done different ways depending on how many phases there are. Generally you use a combination of a ripple counter or johnson counter with some logic gates. There are also special ICs that are specialized for making phase interleaved clocks (look up LTC6902 and LTC6909).

Second, you're going to run into a lot of trouble if you actually try to build this circuit... those FETs are going to pop in seconds. At 50KHz you could get maybe 50A through them reliably. And you have 4V of headroom on Vds, so even under light load they're fail due to avalanche eventually. You should choose some FETs rated at 150V or more and use more phases (four at least), and possibly reduce your switching frequency.

mtwieg,

Thanks for your response. Based on your recommendations, i am now considering IXFK170N20P as my Power MOSFET with 170A and 200V

I am trying to reduce the number of phases due to complexity.

Please look at the attachment below, i am not clear on how to connect the LTC6902 to the driver or the clock sequence. For 2-Phase, my OUT1 & OUT2 of LTC6902 will go to the gate driver HIN & LIN, am i right? While the output of the gate driver HO & LO will go to the upper and lower Power MOSFET of thesame phase, am i right?

Do i repeat thesame sequence for the second phase? I am scared of the two upper MOSFET will be ON at thesame time.

Please advise.

Many thanks,
Ibrahim.

- - - Updated - - -

First of all, if you are using interleaved phases then you must use a current mode control scheme, meaning you do not actually generate PWM with variable duty cycle, but rather you just provide a clock, and the current control loop will settle on a duty cycle based on the peak current setpoint. So you only need to create phase interleaved clocks (not interleaved PWM). This can be done different ways depending on how many phases there are. Generally you use a combination of a ripple counter or johnson counter with some logic gates. There are also special ICs that are specialized for making phase interleaved clocks (look up LTC6902 and LTC6909).

Second, you're going to run into a lot of trouble if you actually try to build this circuit... those FETs are going to pop in seconds. At 50KHz you could get maybe 50A through them reliably. And you have 4V of headroom on Vds, so even under light load they're fail due to avalanche eventually. You should choose some FETs rated at 150V or more and use more phases (four at least), and possibly reduce your switching frequency.

mtwieg,

Thanks for your response. Based on your recommendations, i am now considering IXFK170N20P as my Power MOSFET with 170A and 200V

I am trying to reduce the number of phases due to complexity.

Please look at the attachment below, i am not clear on how to connect the LTC6902 to the driver or the clock sequence. For 2-Phase, my OUT1 & OUT2 of LTC6902 will go to the gate driver HIN & LIN, am i right? While the output of the gate driver HO & LO will go to the upper and lower Power MOSFET of thesame phase, am i right?

Do i repeat thesame sequence for the second phase? I am scared of the two upper MOSFET will be ON at thesame time.

Please advise.

Many thanks,
Ibrahim.

 

[Ogbachi]

All,

Please, i need your help on the clock sequence as in the previous post and attachment.

Thanks,
Ibrahim.

 

[FvM]

According to your initial specification, you need a variable duty cycle to handle the input voltage range. I presume, you'll also want voltage regulation and a current limit function. For optimal operation of the H-bridge, adjustable deadtime is suggested. LTC6902 doesn't provide any of these features.

IR2101 doesn't deliver sufficient gate current for fast switching in the 100 A range. Stronger gate drivers or discrete current booster transistors are necessary.

Although two pairs of IXFK170N20P can theoretically handle the power, the Rds related losses will be unconviently high and e.g. demand for large heatsinks. A reasonable design optimum will require more transistor area.

 

[Ogbachi]

According to your initial specification, you need a variable duty cycle to handle the input voltage range. I presume, you'll also want voltage regulation and a current limit function. For optimal operation of the H-bridge, adjustable deadtime is suggested. LTC6902 doesn't provide any of these features.

IR2101 doesn't deliver sufficient gate current for fast switching in the 100 A range. Stronger gate drivers or discrete current booster transistors are necessary.

Although two pairs of IXFK170N20P can theoretically handle the power, the Rds related losses will be unconviently high and e.g. demand for large heatsinks. A reasonable design optimum will require more transistor area.

FvM,

Thanks for your response. Please advice me on the driver to deliver sufficient gate current for fast switching 100 A range and PWM generator that will output two PWM of 180 degrees out of phase with adjustable dead time. I have searched and i don't know the one to select.

Thanks for you input.
Ibrahim.

 

[mtwieg]

According to your initial specification, you need a variable duty cycle to handle the input voltage range. I presume, you'll also want voltage regulation and a current limit function. For optimal operation of the H-bridge, adjustable deadtime is suggested. LTC6902 doesn't provide any of these features.

As I said above, it just provides interleaved reference clocks to the CMC loops. Gate drive is a completely different issue.

Ogbachi you need to read up on basic current mode control theory. Study **broken link removed** until you understand the current-mode-control loop operation and how it applies to interleaved converters.