PWM Encoder (in VHDL)

PWM_encoder · Sep 23, 2005

pwm encoder

Hi! I don't have a background on VHDL/FPGA until last month when i started to self-study because there is a design contest in our school. Part of the contest is designing a PWM Encoder having 8 bits of input from an ADPCM Decoder and the PWM Encoder is fed with a PCM. The output of the PWM Encoder is also 8 bit. I encountered a program in the net for a PWM Encoder and i can't quite comprehend what most of it is about, which parts fit my specs and all that... can someone help me please?

entity PWM is
Port ( clk : in std_logic;
PWM_in : in std_logic_vector (7 downto 0) := "00000000";
PWM_out : out std_logic);
end PWM;

architecture PWM_arch of PWM is
signal PWM_Accumulator : std_logic_vector(8 downto 0);
begin
process(clk, PWM_in)
begin
if rising_edge(clk) then
PWM_Accumulator <= ("0" & PWM_Accumulator(7 downto 0)) + ("0" & PWM_in);
end if;
end process;
PWM_out <= PWM_Accumulator( 8 );
end PWM_arch;

PWM Encoder (in VHDL)

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PWM Encoder (in VHDL)

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