Easy peasy
Advanced Member level 6
A short article on the design of the push-pull transformer:
These are very problematic for newbies in power electronics,
principally because in a classic topology there are 2 issues that dominate, namely;
1) leakage inductance &,
2) flux balance in the core - i.e. stair-casing of flux / Imag to failure.
Many newbies simply can't appreciate the effect of leakage, or coupling, from the two pri windings to each other - and/or to the output winding ( if there is one ).
Addressing 1): Reducing leakage requires a fundamental understanding of transformer design & construction - multi layering (interleaving - with careful choice of wire sizing) to reduce proximity effect and to lower Llk - and how this - when done well on the primaries - leads to vastly reduced turn off stress (on the mosfets) as the current at turn off can now commute easily & quickly to the other fet (backwards) leading to improved behaviour (see more below**).
Reducing leakage to the output winding(s) has a marked effect on power transfer and wire losses in the Tx, lower leakage = higher coupling = lower proximity effect in the wires = cooler wire temps = maximal power flow for given Cu area.
Too high a leakage L prolongs the time the current takes to (reverse &) ramp up in the secondaries - and so effectively reduces the actual power pulse width seen at the secondary - reducing maximum power transfer for that design.
High Llk also increases stress on the output rectifiers - requiring larger heat dissipating RC snubbers to keep Vrev-pk under control.
Addressing 2): Flux balance in a push-pull requires that the peak flux B, is about the same for each excursion - and does not run way ....
This is pretty easy to do (approximately) in a peak current mode design as the [load-I + Imag] is measured in a CT or common source resistor and the fets are turned off when a pre-determined current level is hit.
In reality, because Imag is not directly controlled, the locus of the magnetising flux excursion ( the B-H loop in the core ) can bounce around a fair bit from near saturation one way to ditto the other way - when it does get near sat one way it tends to help trip the peak current circuit a bit earlier, shortening the "volt.seconds" applied to the core in that direction thus a negative feedback occurs (self correcting - which is why pk I mode works).
This B-H loop meandering is sometimes why you can hear random noise in a push-pull Tx. Slope compensation of the peak current mode signal assists in keeping the B-H locus more bounded - and gives less of the pseudo-random bouncing around ...
But - what do you do for a non peak I mode design? Well you are kinda in trouble, what you can do is:
* make everything as symmetric as possible - on both sides of the Tx...!
* make the Tx symmetric too - in every detail...! ( and the fets ... )
* try to keep noise out of your controller - esp the ramp - or do a discrete design where all the signals are larger and thus much more immune.
* keep the magnetics as far away from the control as possible...!
* Use a fair amount of dead-time in the control** this with low pri leakage allows the Tx windings to fly-back quickly & self-reset, applying opposite volt.seconds to the core in the dead time which works to restore the centrality of the B-H loop.
* Have a decent output choke that does not saturate even under start-up and/or transient overload conditions.
* Don't skimp on Tx design - keep the Bpk well away from the B saturation point at 100 deg C...!
* Use input voltage feed-forward on the ramp - due to the reflective action of the power stage - if the Vin goes up - so does the current (including Imag) - so modulating the ramp with Vin helps (just use Vin on a resistor string to provide the current for the ramp cap). Also gives way better 100/120Hz line rejection.
* OK - you can gap the core too - but the Imag goes up - heating the copper a little - and this approach is just a wee bit agricultural - in the view of some. It really relies on the increased Imag causing I^2R losses, IR drop, in the pcb wiring, fet R etc ... to work.
* Another agricultural approach is source resistors - they reduce gate drive as the Tx tends towards saturation - a somewhat inelegant feedback effect - but it does work.
Lastly - if you have access to pri current information - use it..! add it to the ramp to help keep Bmax bounded - of course if you have this current information you might as well run a peak I - mode - but there it is
These are very problematic for newbies in power electronics,
principally because in a classic topology there are 2 issues that dominate, namely;
1) leakage inductance &,
2) flux balance in the core - i.e. stair-casing of flux / Imag to failure.
Many newbies simply can't appreciate the effect of leakage, or coupling, from the two pri windings to each other - and/or to the output winding ( if there is one ).
Addressing 1): Reducing leakage requires a fundamental understanding of transformer design & construction - multi layering (interleaving - with careful choice of wire sizing) to reduce proximity effect and to lower Llk - and how this - when done well on the primaries - leads to vastly reduced turn off stress (on the mosfets) as the current at turn off can now commute easily & quickly to the other fet (backwards) leading to improved behaviour (see more below**).
Reducing leakage to the output winding(s) has a marked effect on power transfer and wire losses in the Tx, lower leakage = higher coupling = lower proximity effect in the wires = cooler wire temps = maximal power flow for given Cu area.
Too high a leakage L prolongs the time the current takes to (reverse &) ramp up in the secondaries - and so effectively reduces the actual power pulse width seen at the secondary - reducing maximum power transfer for that design.
High Llk also increases stress on the output rectifiers - requiring larger heat dissipating RC snubbers to keep Vrev-pk under control.
Addressing 2): Flux balance in a push-pull requires that the peak flux B, is about the same for each excursion - and does not run way ....
This is pretty easy to do (approximately) in a peak current mode design as the [load-I + Imag] is measured in a CT or common source resistor and the fets are turned off when a pre-determined current level is hit.
In reality, because Imag is not directly controlled, the locus of the magnetising flux excursion ( the B-H loop in the core ) can bounce around a fair bit from near saturation one way to ditto the other way - when it does get near sat one way it tends to help trip the peak current circuit a bit earlier, shortening the "volt.seconds" applied to the core in that direction thus a negative feedback occurs (self correcting - which is why pk I mode works).
This B-H loop meandering is sometimes why you can hear random noise in a push-pull Tx. Slope compensation of the peak current mode signal assists in keeping the B-H locus more bounded - and gives less of the pseudo-random bouncing around ...
But - what do you do for a non peak I mode design? Well you are kinda in trouble, what you can do is:
* make everything as symmetric as possible - on both sides of the Tx...!
* make the Tx symmetric too - in every detail...! ( and the fets ... )
* try to keep noise out of your controller - esp the ramp - or do a discrete design where all the signals are larger and thus much more immune.
* keep the magnetics as far away from the control as possible...!
* Use a fair amount of dead-time in the control** this with low pri leakage allows the Tx windings to fly-back quickly & self-reset, applying opposite volt.seconds to the core in the dead time which works to restore the centrality of the B-H loop.
* Have a decent output choke that does not saturate even under start-up and/or transient overload conditions.
* Don't skimp on Tx design - keep the Bpk well away from the B saturation point at 100 deg C...!
* Use input voltage feed-forward on the ramp - due to the reflective action of the power stage - if the Vin goes up - so does the current (including Imag) - so modulating the ramp with Vin helps (just use Vin on a resistor string to provide the current for the ramp cap). Also gives way better 100/120Hz line rejection.
* OK - you can gap the core too - but the Imag goes up - heating the copper a little - and this approach is just a wee bit agricultural - in the view of some. It really relies on the increased Imag causing I^2R losses, IR drop, in the pcb wiring, fet R etc ... to work.
* Another agricultural approach is source resistors - they reduce gate drive as the Tx tends towards saturation - a somewhat inelegant feedback effect - but it does work.
Lastly - if you have access to pri current information - use it..! add it to the ramp to help keep Bmax bounded - of course if you have this current information you might as well run a peak I - mode - but there it is