module main (button, userclock,sevenLed,cathode);
input [1:0] button;
input [0:0] userclock;
output [6:0] sevenLed;
reg [6:0] sevenLed;
output [0:0] cathode;
reg [3:0] numSelect;
reg [3:0] out ;
reg [3:0] out2;
wire [3:0] wout;
wire [3:0] wout2;
clk_divider cd(userclock,cathode); //divides the clock
counter counter(button, wout, wout2); //does the counting
//always@(userclock) begin
//out=wout;
//out2=wout2;
//end
always @ (posedge userclock) begin
out<=wout;
out2<=wout2;
end
always @(userclock) begin //what side to show?
if (cathode==0)
numSelect=out;
else
numSelect=out2;
end
always @(posedge userclock) //output to the 7segment display
case (numSelect)
0: sevenLed = 7'b0111111;
1: sevenLed = 7'b0000110;
2: sevenLed = 7'b1011011;
3: sevenLed = 7'b1001111;
4: sevenLed = 7'b1100110;
5: sevenLed = 7'b1101101;
6: sevenLed = 7'b1111101;
7: sevenLed = 7'b0000111;
8: sevenLed = 7'b1111111;
9: sevenLed = 7'b1100111;
10: sevenLed = 7'b1010101;
default sevenLed=0;
endcase
endmodule