Pure stable clock source - clock source may be unstable

[nemolee]

Pure stable clock source

Hi, I had a problem in my system. The clock source may be unstable. This unstable clock source cause my system to output garbage data. Although my design system can be recovery after clock is stable. But my customer argue this problem. I have to design a robust system to meet their reqiurement.

I want to design a clock detector to watch input clock at front end of my system.
If input clock is unstable, this detection circuit can block clock and doesn't output any clock. If clock source is stable, detection circuit can know current state and doesn't block clock and bypass input clock.

Does anyone can tell me how to design this digital circuit by verilog code ?
PS: There is one oscillator in my system.
Thank you very much.

 

[rberek]

Re: Pure stable clock source

First of all, define "unstable".

Secondly, if you only have one clock in the system, the circuit you design to detect an unstable clock is itself clocked with that unstable clock. I'm not sure that is a workable situation. If you really want to detect clock instability, you would need detection circuitry clocked with a clean, known-good reference clock.

I personally haven't seen this sort of circuitry used. Instead, why don't you work on making your clock stable?

r.b.

 

[FvM]

Pure stable clock source

I also think, your specification is too vague, yet. There may be different kinds of clock instability, with different impact on system behaviour.

As said, there are very limited options to detect clock instability (however you specify it) without a reference clock. On the other hand, some types of clock sources, e. g. crystal oscillators, can be regarded inherently stable.

In some cases, a PLL lock detector may be a sufficient indicator for a stable clock.

 

[nemolee]

Re: Pure stable clock source

Unstable means that clock frquency changes hugely sometimes.
In my design, there is one stable clock, oscillation clock.
I can use it to detect input clock.
But I don't know what design is good or how to design a good detection circuitry. This detection circuitry doesn't have erroneous judgement. The stable clock is deemed a good clock, not bad clock.
Thank you.

 

[rberek]

Re: Pure stable clock source

OK, I'm still not clear here. I thought you had one clock, but now it appears you have two.

So, if you have a stable clock in the system, why are you using an unstable clock as your input clock? Why don't you use the stable clock as your source? You can always use a PLL to generate different frequencies or phases from it should you need to.

r.b.

 

[littlebu]

Pure stable clock source

hi, nemolee
maybe you can give us some detail about this two clocks, like source and relationship with each other.

why you can't sure input clock more stable?

R&B
littlebu