Sep 28, 2006 #1 E ei99dami Newbie level 4 Joined Sep 26, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,336 Hi, Is it possible to create a 10 MHz pulse width modulated signal from a FPGA? /Robin
Sep 28, 2006 #2 gliss Advanced Member level 2 Joined Apr 22, 2005 Messages 691 Helped 75 Reputation 150 Reaction score 16 Trophy points 1,298 Activity points 5,892 Of course. What FPGA are you using?
Sep 29, 2006 #3 E ei99dami Newbie level 4 Joined Sep 26, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,336 The FPGA is a Altera Stratix II or Virtex 4. The resolution for the 10 MHz signal is 2^8. (clk in to FPGA will be 2550 MHz) That will be a problem. /Robin
The FPGA is a Altera Stratix II or Virtex 4. The resolution for the 10 MHz signal is 2^8. (clk in to FPGA will be 2550 MHz) That will be a problem. /Robin
Sep 30, 2006 #4 R rancohen_2000 Advanced Member level 4 Joined Aug 24, 2006 Messages 119 Helped 23 Reputation 46 Reaction score 1 Trophy points 1,298 Activity points 1,958 you can use the PLL in the FPGA to reduce the CLK. and then use logic do set your pulse pattern
Oct 2, 2006 #5 E ei99dami Newbie level 4 Joined Sep 26, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,336 Can you please evolve what you mean with the PLL and how to implement the logic and set up your pulse pattern. /Robin
Can you please evolve what you mean with the PLL and how to implement the logic and set up your pulse pattern. /Robin