pulse detector-verilog

[shiva20587]

Hi,,
I need to design a pulse detector system which senses the input pulses and outputs a BCD digit,1. The input to the system is a pattern of pulse sequence with 60 msec ON followed immediately by 40 msec OFF. (Used in old telephone pulse dialing systems). The system counts such continuous pulses to detect a dialed number.
How to generate that waveform with 60% duty cycle using verilog???

 

[lucbra]

Just sample the input with 100kHz. You will be able to find the rising edge and falling edge of the signal. The rest is a matter of counting ...

... or you can use the input as an enable for a 100kHz counter - which is almost the same as the above ...