Accoring to kT/C noise theory,
I expect to noise power as much as 37.692nV2/Hz because of 100fF load capacitance.
However, the simulation results shows just 0.3464fV2/Hz at flat zone (white noise by thermal) like
The mean of "Integrate regarding frequency" is like this?
However, In my case, the integrated noise power is changed according to range of integration.
First, in my opinion, the integrated noise power is limited at some frequency because of low pass filter of switch and load capacitor. However, the integrated noise power is increased constantly. Is it right?
Second, if it is right, How much I should set the range of frequency when I integrate the noise ?
I tried to measure kT/C noise in the circuit you provided but got strange results and it did not converge.
I have attached a simple low pass filter, where we have two switches and a capacitor. The clock frequency is 10Mhz so the equivalent resistance should be approx 1Mohm with a 100fF cap. With a 1pF cap the pole should be at aprox 160kHz. I used complementary switches and non overlapping clock signals.
The noise is aprox 20nV/sqrt(Hz) so it is close to the theoretical calculation.
Hope this helps.