Hi Shanmei,
In fact, it was just something I thought based on your question. However, I thought better and I think I have a better answer for you.
In Gray and Meyer's paper, they are considering the PSRR from V-, what makes me think that the ground there can be considered as a static reference for the whole circuit. It said, in fact this ground connection at PMOS gate does not jeopardize your negative PSRR.
In the schematic I shared, the left side of the capacitor is not well defined and mismatch between the current sources could drive some of those devices to triode region, therefore maybe is better you disregard it (sorry about that...).
What I can suggest, if the PMOS does not fit connected to ground, is a "level shift" from output's reference node (keep in mind that this output will be always "referred" do some other voltage node).
I hope this can help you.
Best regards!
Vitor