TI recommends adding at least 1V to the ramp signal to prevent asymmetry in CD pulses. Application Report SLUA275 - September 2002. So I am using 3 resistors to add 2/5 of the current signal, 2/5 of the compensation ramp, and 1/5 of the ref voltage (1/5*5=1V).why is R6 in your ckt ? ( slope comp / curr sense )
CT core is B64290-L45-X38, T38, R16х9.6х6.3, (Ae approx 20mm^2) 1 turn on the primary and almost 100 on the secondary. I also tried different materials (n87) but the signal shapes were the same on both CT's. The current transformer ring is located approximately 20 mm from the corner of the power transformer.Need to know much more about the CT ( design )
The secondary side of the transformer layout is as symmetric as possible, output diodes connected almost at transformer pins and caps are almost on the diodes. Diodes are on the same heatsink.if the secondary side of the transformer layout is assymetric ( imbalance of leakage L ) / messy - including through the diodes to the output caps, then you will get an imbalance of volt seconds referred to the primary,
esp if the forward drop of the output rectifiers is different - i.e. they are differently heatsunk
As we cannot see how you transformer is made, nor can we see the physical layout - we cannot comment further
Is it possible that I have too much slope compensation to balance the flux or my output inductor is too small? Is there any rule of thumb for the ratio of the current slope / compensation slope?and some information about the slope comp you are using to stabilise the system above 45% phase shift
I have actually built a simplified model of my converter. Model was simplified in a sense that I have not modeled the exact PWM IC behaviour and feedback circuitry. Also as my basic model don't include modeling of the saturation phenomenon of magnetics it has little use now. I think I nedd to find UC3895 spice model first to improve my model.I implore you to go to the LTspice simulator first......get it workigng in LTspice...only when you have it working there, do you go to the bench.
Simulator is not real...but there is a rule of electronics...."if you cannot get a representation working on the simulator first, then you will never get it working on the bench"
--- Updated ---
here is LTspice sim of PSFB
97 turns on the secondary.sorry - how many on the secondary ? 50, 60, 70, 80 90 ?
Just for simplicity now. In real design I am using a voltage divider from RAMP pin to CS to fine tune current protection trip.Why have you tied CS to Ramp in the schematic ?
At around 800W ZVS on QC QD was achieved. But I will put the same caps as QA QB to check if it is the reason for imbalance.The 1N caps across QC1, QD1 are likely excessive, try same as other leg
Bypassing these pins to gnd creating a huge jitter in the gate signals and also greatly increase IC current consumption (+ ~20%). In the starting design I had 10n there. As soon as I removed caps, signals became stable like never before.pins 9 and 10 could do with 4n7 to gnd right by their pins
Oops... I will revisit these capacitors and increase summing resistors value to lower ref load.no more than 1uF - not the 4uF you show on your schematic
Since my D105,D106 is TO263 it will be pretty hard mod to do... I tried to add resistors in siries with these diodes on a previous PCB, but losses were just too high. And if these diodes can't affect on a symmetry in the primary current and just increase some EMI I prefer left it as it is for now.Also - you really should have a damping resistor associated with the diodes D105, 106 - you can see the horrendous current ringing you get without such R
My circuit is utterly simple. It contains 3 fixed resistors R4, R7, R6 such that R6=2R4=2R7. This gives us summing ratios of 2/5 of signal behind R4 (signal from CST), 2/5 of signal behind R7 (compensation slope), and finally 1/5 of the signal behind R6 (ref voltage). To keep everything simple these ratios are fixed. R6 gives us 1V of dc bias to the ramp signal and does not introduce any slope changes so it can be ignored.If you want to use your extant ckt - you can do the calcs to level shift according to all the extra resistors you have thrown in.
I doubt there is such a thing as an ideal transformer in real world applications. There are no practical possibilities to make two windings exactly the same. There always will be differences in the windings or in layout.you internal transformer construction is not really that symmetric - thus you will get different leakages on the sec wdgs when you short the pri
this is probably the fundamental cause of the flux walking in the Tx as it effectively providing different " drive " to each sec and hence a different reflected V.sec to the core on each half cycle.
Gapping the core is likely your best cure here - along with fixes listed above.
I didn't post PCBs mainly because I have already made some changes to it. So It can be quite confusing. Please note, that the actual schematic is attached to the first post.Finally - layout plays a huge issue and we cannot see the finished physical embodiment you have created.
Hello! Yes, I think I found the problem. The current transformer in series with the main Tx was the reason for the main transformer saturation. I think that DC current information was lost due to current transformer (CT) placement. This small DC current probably moved the BH curve of the main transformer closer to saturation. Since I replaced the current transformer and put it on the input bus, the problem has disappeared. I didn't change CT material, or slope compensation parameters. Just the placement of the CT makes a difference.@Porsche Did your problem got resolved? I am facing same issue. Same waveform of Transformer. If it is solved, can you please update, how it got resolved. Thanks in Advance!
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