[SOLVED] Project to replace CY7C64613 in the ICD2

[around]

Problem solved.

I changed out the 877A for an 877 and used the 877 bootloader file from MPLAB. After that everything worked fine.

Cheers,

Adrian

 

[polymath]

Hi NICK7

Glad to hear of your success, but I am wondering why you have resistors on the OUTPUT of your buffers?
Original had NO resistors on Buffer Outputs - but it did have them on the inputs to protect them from being over-driver by 877A when target Vdd was low (the buffer supply comes from target Vdd).
The output of the buffers is limited to 20mA and short circuit tolerant for 5s.
If you are concerned about protection have you considered polyfuses on the outputs?


Hi around
It appears that you have missed al the postings about the two different bootloaders for the 877 and one for the 877A. They are NOT interchangeable.

My preference is for the 877A - it is much much faster when downloading a new OS - and ALWAYS use the 877A as a development target in preference to the sluggish 877 (now obsolete).

To experience the difference program an 877 target in Debugger with a large program image - then do the same with an 877A target - remember to select the correct device! Wow - what a difference!


well done ... Polymath

szlovak
I see another of your posts is incomprehensible - read the thread - write meaningful posts.
To whom are you replying - what are you writing about - are you just posting to raise points?

Polymath

 

[NICK7]

Hi Polymath
Firstly thanks for you comments. Secondly do you know how mplab controls the Vpp via the digital pot? I am running MPLAB 7.30 and no menu is relative to this function.
Nick

 

[polymath]

Hi NICK7

The +VHH is controlled automatically by MPLAB & ICD2 in harmony!
Have a look on:
**broken link removed**
- page 20 of this thread - what not reading postings!!!

The digital pot DPOT is BitBanged SPI controlled by 877A.
The +VHH which it sets depends upon the Device YOU select and this is why the warning about Device Expected = ??? Device Found = ??? is important - I would suggest you do NOT suppress it.
Control value 0xFF is MIN +VHH, 0x00 is MAX +VHH
Depending on the OS downloaded the pot is ramped down or up until RA0 reads the correct +VHH value.
When the correct value is reached then DG411 can apply it to Target-Vpp pin.
Note:
If DG411 is not used and Target-Vpp pin cannot be driver Hi-Z there is a chance that target will receive an over-voltage whilst pin is ramped. This is of concern when using low Vdd and PIC24/dsPIC 3v3 devices. The ICD2 does not normally use +VHH for 3v3 devices - they only require +VH (+Vdd) for programming.

regards ... Polymath

 

[Hal]

It is possible that they used 2 switches in parallel for 13V to reduce resistance

simply to put ADG451 or ADG431 ...

 

[potyo]

Why using DG411 is better than using transistors? I see differences only in the used space(DIL14+4*Res vs. DIL14+3*Res+2*TO92) if we use series resistor(50-100Ω) to avoid latch-up.

 

[polymath]

Hi Hal
here is an extract from 877A data sheet:

2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100? should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS.

The DG411 has an Ron of 35Ω - ICD2-Original works fine with value.
Going to a lower value of 5Ω (ADG451) as you suggest my cause latch-up problems per MChip warning. Your choice!


regards ... Polymath

 

[around]

Polymath,

Thanks for the feedback. I was using an 877A bootloader from the files that PICS provided. I will try some of the other 877A bootloader files on the forum and see if I can get it to work with an 877A. I was just happy to get it to work (11PM) after a frustating day of not getting anywhere!

Update 13 July: I was using an early version of the 877A during my initial attempts to get the ICD2 to work. After receiving a currrent rev 877A from Microchip, I was able to burn the bootloader, download the OS and use the ICD without any problems.

Cheers,

Adrian

 

[R2D1]

This thread is so active, need to catch up.

Polymath:
Thanks for the link. The design of 0430_004 is not optimized (such as NAND gate), I can believe it is the first clone, but can't believe it as the original circuit.

The 3.3V debug thread is a good one, the choice of different logic family and use of ISPVDD is well explained, worth reading.

BTW, you may better get an isolation transformer for your soldering iron. I did consider the isolation possibility, but a VR tuned VPP design already take 3 opto coupler + 2 isolator. After consideration, auto VPP setting is more important than isolation to me.

Target-Vpp pin cannot be driver Hi-Z

The transistor can be switched off, take lothar's design as example:
**broken link removed**
If RC0 > VDD-0.6V, T1 turn off -> T2 turn off. MCLR pin will not see VPP.

Potyo:
I think analog switch is only better if you release your design for others to build. For any transistor you choose, it will not be available at other part of the world. And beginners will have problem choosing substitute, or inserting the wrong pin in their assembly.

Questions:
Anyone know why the Target PGD need to connect to RC4 & RC5 (2 pin), while Target PGC only connect to RC3 (1 pin).

The 0430_004 design have circuit to drive pin 6 of the target connector. Is function of pin 6 documented?

 

[polymath]

Hi potyo

Why using DG411 is better than using transistors? I see differences only in the used space(DIL14+4*Res vs. DIL14+3*Res+2*TO92) if we use series resistor(50-100Ω) to avoid latch-up.

If you use the DG411, Target Vpp can be placed in Hi-Z so that the target running under its own PSU and reset circuit will not be affected in any way.
The PGD & PGC if buffered as ICD-Original also go to Hi-Z.
This automatically isolates target when running.
Less components means less opportunities for build faults.

As you know, all this already been said on 3.3V PIC24 thread:


regards ... Polymath

Added after 1 hours 7 minutes:

Hi R2D1

This thread is so active, need to catch up.

BTW, you may better get an isolation transformer for your soldering iron. I did consider the isolation possibility, but a VR tuned VPP design already take 3 opto coupler + 2 isolator. After consideration, auto VPP setting is more important than isolation to me.

Target-Vpp pin cannot be driver Hi-Z

The transistor can be switched off, take lothar's design as example:
h**p://home.vrweb.de/~lotharstolz/stolz.de.be/icd/text02.html
If RC0 > VDD-0.6V, T1 turn off -> T2 turn off. MCLR pin will not see VPP.

I thought I saw a potential divider from Target Vpp which feeds RA0 with an impeadance of less than 10k - perhaps you think 10k is Hi-Z? No?

The matter of the buffers and NAND gates. The buffers are all 74HC126 and the NAND used for direction control & input res.
Another design **broken link removed**
uses 74AHC125 & 126 & NAND & input res & output res.
In production the saving of one chip type is desireable. minimise component variants, part numbers & production errors, doubles bulk purchase power.
The second design uses two buffer types simplifies direction control BUT requires NAND gate for logic function - no advantage - the designer also put res. on inputs of 74AHC which Potyo pointed out are not necessary as AHC have 5v0 tolerant inputs. The buffer output res. are far too high - actually not needed.

Transistor controlled Vpp:
Fine - mine works - MChip even have a design for one
**broken link removed**

If the MCLR pin does not rise fast enough, while the device’s voltage is in the valid operating range, the internal Program Counter (PC) can increment. This means that the PC is no longer pointing to the address that you expected to be at. The exact location depends on the number of device clocks that occurred in the valid operating region of the device.

As to the RC4 & RC5 question - I do not yet know why.

Pin6 is RB3 Low Voltage Programming enable pin - see 877A data sheet

best regards ... Polymath

 

[R2D1]

Polymath:

I quote the wrong phrase.

Target-Vpp pin cannot be driver Hi-Z there is a chance that target will receive an over-voltage whilst pin is ramped

What I mean is the target will not see the VPP when it ramp up/down as long as the transistor is off, so no risk of damage from transistor circuit. I agree the DG411 is better, but those already built the transistor design should not be worried.

The second design uses two buffer types simplifies direction control BUT requires NAND gate for logic function - no advantage

You are right, I compare to the wrong circuit - Potyo's design. Which do not implement target pin 6, so the NAND gate is missing.

Pin6 is RB3 Low Voltage Programming enable pin - see 877A data sheet

This is true for ICD1 connector. Refer to ICD2 user guide, pin 6 is mark as Not Used (Figure 9-1).

[ICD2 UG Pg. 20] Note: MPLAB ICD 2 does not support Low Voltage Programming. MPLAB ICD 2 will disable this function. You cannot enable it through programming using the MPLAB ICD 2.

I guess it is safe to remove any circuit driving pin 6.

 

[potyo]

The PGD & PGC if buffered as ICD-Original also go to Hi-Z.
This automatically isolates target when running.

Are you sure in it? I have now connected an 580Ω resistor between isp-vdd and pgd pins(target powered from icd2 checkbox was checked), and the current through these resistor was 8mA(4.8V/580Ω≈8mA). So the output was not in HiZ, it was in low state after executing the Read command(Programmer-->Read).

 

[Lothar Stolz]

R2D1:

Questions:
Anyone know why the Target PGD need to connect to RC4 & RC5 (2 pin), while Target PGC only connect to RC3 (1 pin).

I supposed it to be some kind of detection for the bidirectional line being stuck in low/high state (but never investigated to it further!!! just a thought!): for example, if the ICD wants to pull it up via output RC4 (or RC5) and resistor, it would be able to detect stuck state reading input RC5 (or RC4)?!?

Andy_123

- MPLAB downloaded temporary USB bootloader into empty memory area.
- reset - you can hear USB disconnected and re-connected again using temp BL

- using temp bootloader MPLAB erased and downloaded new bootloader
- reset - you can hear USB disconnected and re-connected again using new BL

hmmm... that makes sense. i will take a close look a that as soon as possible (unfortunately, i think not before end of july - i'll have to get home where my attic is first - working without hardware in hands doesn't make fun...) and let you know what i could find out!


concerning the dc/dc-converter-design-process:
perhaps take a look at SwitcherCAD from LT, is a very good SPICE-simulator (helpfull for stability, various load situations, startup, etc.) It's for free. I like it better than PSpice!

There is also some application note from microchip about a pic-boost-converter (it's about driving a pixie-tube-display)- i don't have the link at the moment, but google surely will do. However, I didn't consider it was very usefull to me...

 

[willib]

here it is.
https://ww1.microchip.com/downloads/en/AppNotes/91053b.pdf

 

[Mike K8LH]

I'm just about to start playing with the 12F683 Boost design after studying the formulas in a spreadsheet. Seems output current is mostly a factor of Inductor peak current.

How much current should the boost regulator provide with 10v to 13v output? It looks like I could use a couple candidate inductors here on the Lab bench. A nice small Fastron 220uh/130ma radial is good for 25ma @ 13v. A resonably compact C&D 68uh/770ma vertical is good for 148ma @ 13v. Can we get away with the small radial and 2N3904 transistor low current design? If so, would that limit it to Flash only devices (no old 16C' devices)?

Should I start a new thread/topic for this potential ICD2 controlled variable 12F683 boost regulator experiment?

Kind regards, Mike

 

[potyo]

Here is one nice calculator for designing boost regulator: **broken link removed**

 

[namqn]

concerning the dc/dc-converter-design-process:
perhaps take a look at SwitcherCAD from LT, is a very good SPICE-simulator (helpfull for stability, various load situations, startup, etc.) It's for free. I like it better than PSpice!

Yes, I agree with you!

Cheers,

 

[potyo]

Anybody knows the clock frequency on the DPOTs SPI bus, when 877 changes the vpp voltage?

 

[polymath]

Hi potyo

Have a look at ICD????.Hex OS in ICD2 directory - [they are all for 877(A)]
All the files I have looked at are bit-banged SPI.
Here is an example from ICD08010500.hex:

  Line   Addr  Opcode  Disassembly                 
   600   0257   3008    MOVLW 0x8
   601   0258   00D0    MOVWF 0x50
   602   0259   0DD7    RLF 0x57, F 
   603   025A   1C03    BTFSS 0x3, 0
   604   025B   2A5E    GOTO 0x25e
   605   025C   1786    BSF 0x6, 0x7
   606   025D   2A5F    GOTO 0x25f
   607   025E   1386    BCF 0x6, 0x7
   608   025F   0000    NOP
   609   0260   0000    NOP
   610   0261   0000    NOP
   611   0262   0000    NOP
   612   0263   1706    BSF 0x6, 0x6
   613   0264   0000    NOP
   614   0265   0000    NOP
   615   0266   0000    NOP
   616   0267   0000    NOP
   617   0268   1306    BCF 0x6, 0x6
   618   0269   0BD0    DECFSZ 0x50, F
   619   026A   2A59    GOTO 0x259
   620   026B   0008    RETURN
   621   026C   1486    BSF 0x6, 0x1
   622   026D   1706    BSF 0x6, 0x6
   623   026E   1786    BSF 0x6, 0x7
   624   026F   0008    RETURN
   625   0270   1486    BSF 0x6, 0x1
   626   0271   1706    BSF 0x6, 0x6
   627   0272   1386    BCF 0x6, 0x7
   628   0273   0008    RETURN
   629   0274   1486    BSF 0x6, 0x1 *****duplicate code
   630   0275   1706    BSF 0x6, 0x6
   631   0276   1386    BCF 0x6, 0x7
   632   0277   0008    RETURN

It is an asymmetrical clock with 5, 7 or 8 instructions between SCK and SI transitions depending on the bit being sent - poor coding!

There appears to be some duplicate code in this Hex at line 629
All the Hex files I have looked at have this duplicate code so I would assume that the SPI routine is the same for all Hex OS files.

regards ... Polymath

 

[R2D1]

Lothar:

Thanks for the idea, but the technique could not be used with the buffer in place. When the buffer switched to out direction, the 877 will read the state of buffer input, rather than the state of the target PGD.

Could it be for satisfying the PGD setup time using hardware? So as to simplify the 877 code. :roll: