Jul 2, 2009 #1 K kandaka Newbie level 4 Joined Feb 19, 2007 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,313 verilog projects Hi, I am planing to develop System Verilog environment for any application from stratch.So,Can anyone suggest me something regarding this. Thanks in advance.
verilog projects Hi, I am planing to develop System Verilog environment for any application from stratch.So,Can anyone suggest me something regarding this. Thanks in advance.
Jul 2, 2009 #2 J jimjim2k Advanced Member level 3 Joined May 17, 2001 Messages 996 Helped 23 Reputation 46 Reaction score 13 Trophy points 1,298 Activity points 7,178 system verilog projects Hi R u mean IDE for systemVerilog? tnx
Jul 3, 2009 #3 S sivamani Full Member level 6 Joined Jan 30, 2007 Messages 336 Helped 46 Reputation 92 Reaction score 43 Trophy points 1,318 Location Hyderabad Activity points 2,919 verilog project Can you pls elabarate further.........
Jul 3, 2009 #4 K kandaka Newbie level 4 Joined Feb 19, 2007 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,313 system verilog project actually i am new to SV and VMM.So planing to develop the environment for any protocal or DUT so that i can use the main features of SV. Please suggest me regarding this
system verilog project actually i am new to SV and VMM.So planing to develop the environment for any protocal or DUT so that i can use the main features of SV. Please suggest me regarding this