programming MFRC522 with hdl

[wowpro7]

Hello,
i am using "RFID-RC522" modules based MFRC522. https://www.nxp.com/docs/en/data-sheet/MFRC522.pdf
i am trying to work with it using HDL programming, in my case Verilog, but i am having hard time configuring it.
i tried to configure it in such way that it will raise IRQ when it read RF-ID, but i have no success.
i would be very thankful your help.
code:

reg [7:0] rAddress = {`READ, 6'h01, 1'b0}; //Read Address 0x01
    reg [15:0] rPackage_to_Send = 8'h08; //Data of the firt 'Write Command'
    reg [31:0] rReading_Data = 0; //UID - Unique Identification ,  4 Bytes of ID from the card, this must be send to the FIFO
    reg sSCK = 0;
  
    assign oSCK = sSCK; //Driving Clock to RFID

always @(posedge iClock) begin // devide clock by 2
      sSCK = ~sSCK;
    end
  
    always @(posedge iClock) begin // working on falling edge, because SPI prefers data being changed when clock at 0 and stable when clock at 1
        if(iReset == 1) begin
                //Reset Registers/Signals
            rCase_Machine <= 0;
            rBits_Counter <= 0;
            rAddress <= {`READ, 6'h01, 1'b0}; //Read Address 0x01
            rPackage_to_Send <= 8'h08;
            rReading_Data <= 0;
          
                //Reset I/Os
            oMOSI = 0;
            oNSS = 1;
            oData = 0;
            oWriteEnable = 0;
            timer_counter = 0;
        end else if (sSCK==1'b1) begin
            case (rCase_Machine)
                (0):  begin // Read Address 0x01 to see if its ready to work
                    if (rBits_Counter<8) begin
                        oNSS = 0;
                        oMOSI = rAddress[7-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else if (rBits_Counter>=8 && rBits_Counter<=15) begin
                        rReading_Data[23-rBits_Counter] <= iMISO; // using 'rReading_Data' as data saving temporary because of the need to save as much space as possible.
                        rBits_Counter <= rBits_Counter + 1;
                    end else begin
                        oNSS = 1;
                        if ((rReading_Data[15:8] & 8'h10) == 0) begin
                            rCase_Machine <= rCase_Machine + 1;
                            rPackage_to_Send[15:0] <= {{`WRITE, 6'h02, 1'b0}, 8'ha0 }; //write Address 0x02, Data: 0xa0
                        end
                        rBits_Counter <= 0;
                    end
                end
                (1): begin //write Address 0x02, Data: 0xa0
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else begin
                        oNSS = 1;
                        rCase_Machine <= rCase_Machine + 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h03, 1'b0}, 8'h80 }; //write Address 0x03, Data: 0x80
                        rBits_Counter <= 0;
                    end
                end
                (2): begin //write Address 0x03, Data: 0x80
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else begin
                        oNSS = 1;
                        rCase_Machine <=rCase_Machine + 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h04, 1'b0}, 8'ha0 }; //write Address 0x04, Data: 0xa0
                        rBits_Counter <= 0;
                    end
                end
                (3): begin //Write Address 0x04, Data: 0xa0
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else begin
                        oNSS = 1;
                        rCase_Machine <= rCase_Machine + 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h0a, 1'b0}, 8'h80 }; //write Address 0x0a, Data: 0x80
                        rBits_Counter <= 0;
                    end
                end
                (4): begin //Write Address 0x0A, Data: 0x80. Reseting FIFO
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end  else begin
                        oNSS = 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h13, 1'b0}, 8'h0C }; //write Address 0x13, Data: 0x0c
                        rReading_Data[15:8] <= 0;
                        rCase_Machine <= rCase_Machine + 1;
                        rBits_Counter <= 0;
                    end
                end
              
                (5): begin //Write Address 0x0A, Data: 0x80. Reseting FIFO
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end  else begin
                        oNSS = 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h17, 1'b0}, 8'h84 }; //write Address 0x17, Data: 0x84
                        rReading_Data[15:8] <= 0;
                        rCase_Machine <= rCase_Machine + 1;
                        rBits_Counter <= 0;
                    end
                end
               (6): begin //Write Address 0x17, Data: 0x84
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end  else begin
                        oNSS = 1;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h01, 1'b0}, 8'h09 }; //write Address 0x01, Data: 0x09
                        rReading_Data[15:8] <= 0;
                        rCase_Machine <= rCase_Machine + 1;
                        rBits_Counter <= 0;
                    end
               end
               (7): begin //write Address 0x01, Data: 0x09, enable receiving data
                        oWriteEnable = 0;
                    if (rBits_Counter<16) begin
                        oNSS = 0;
                        oMOSI = rPackage_to_Send[15-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end  else begin
                        oNSS = 1;
                        rReading_Data[15:8] <= 0;
                        rCase_Machine <= rCase_Machine + 1;
                        rAddress <= {`READ, 6'h07, 1'b0}; // Read StatusReg
                        rBits_Counter <= 0;
                    end
               end
               (8): begin //Wait for IRQ, IRQ = Received Full Data Frame
                    if (iIRQ==1) begin // IRQ == New Data Valid
                        rAddress <= {`READ, 6'h0a, 1'b0}; // Read address 0x0A
                        rCase_Machine <= rCase_Machine + 1;
                        timer_counter <= 0;
                    end
                    else begin // Read StatusReg for IRQ
                        if (rBits_Counter<8) begin
                            oNSS = 0;
                            oMOSI = rAddress[7-rBits_Counter];
                            rBits_Counter <= rBits_Counter + 1;
                        end else if (rBits_Counter>=8 && rBits_Counter<=15) begin
                            rReading_Data[23-rBits_Counter] <= iMISO; // using 'rReading_Data' as data saving temporary because of the need to save as much space as possible.
                            rBits_Counter <= rBits_Counter + 1;
                        end else begin
                            oNSS = 1;
                            if ((rReading_Data[15:8] & 8'h10) == 8'h10) begin
                                rCase_Machine <= rCase_Machine + 1;
                            end
                            rBits_Counter <= 0;
                        end
                    end
                end
              
                (9): begin //Read address 0x0A and see if there is any Data stored in FIFO Recv
                    if (rBits_Counter<8) begin
                        oNSS = 0;
                        oMOSI = rAddress[7-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else if (rBits_Counter>=8 && rBits_Counter<=15) begin
                        rReading_Data[23-rBits_Counter] <= iMISO; // using 'rReading_Data' as data saving temporary because of the need to save as much space as possible.
                        rBits_Counter <= rBits_Counter + 1;
                    end else begin
                        oNSS = 1;
                        if (rReading_Data[15:8] > 0) begin // Dat is not empty
                            rCase_Machine <= rCase_Machine + 1;
                            rAddress <= {`READ, 6'h09, 1'b0};// read address 0x09
                        end
                        else begin //FIFO had no data, enable recveing data frame again.
                            rPackage_to_Send[15:0] <= {{`WRITE, 6'h01, 1'b0}, 8'h09 }; //write Address 0x01, Data: 0x09
                            rCase_Machine <= 6;
                        end
                        rBits_Counter <= 0;
                    end
                end
                (10): begin // read data from Address 0x09
                    if (rBits_Counter<8) begin //Send The Reading Address
                        oNSS = 0;
                        oMOSI = rAddress[7-rBits_Counter];
                        rBits_Counter <= rBits_Counter + 1;
                    end else if (rBits_Counter >= 8 && rBits_Counter <=39) begin // Read the Reading Address
                        rReading_Data[39-rBits_Counter] <= iMISO;
                        rBits_Counter <= rBits_Counter + 1;
                    end  else begin
                        oNSS = 1;
                        rCase_Machine <= rCase_Machine + 1;
                        rBits_Counter <= 0;
                    end
                end
                (11): begin  //Sending Data to FIFO
                    if(i_IsFull==0) begin// i guess its 0 when not full
                        oWriteEnable = 1;
                        oData = rReading_Data;
                        rCase_Machine <= 8;
                        rPackage_to_Send[15:0] <= {{`WRITE, 6'h01, 1'b0}, 8'h09 }; //write Address 0x01, Data: 0x09
                    end
                end
             endcase
      
        end
    end

summary of the code:

1. // Read Address 0x01 to see if its ready to work
2. //write Address 0x02, Data: 0xa0
3. //write Address 0x03, Data: 0x80
4.//Write Address 0x04, Data: 0xa0
5.  //Write Address 0x0A, Data: 0x80. Reseting FIFO
6.//Write Address 0x0A, Data: 0x80. Reseting FIFO
7.//Write Address 0x17, Data: 0x84
8.//write Address 0x01, Data: 0x09, enable receiving data
9.//Wait for IRQ, IRQ = Received Full Data Frame
10.//Read address 0x0A and see if there is any Data stored in FIFO Recv
11.// read data from Address 0x09
12.//Sending Data to FIFO

[Moderator action: corrected formatting tags]

 

[barry]

This is impossible to read.

Please adjust your formatting. Lines like “end else begin” are just horrible. Use indentations (your editor should do it for you). The TAB key is your friend.

 

[FvM]

Generally I'd prefer a more hierarchical structure with SPI read/write performed in separate modules.

Not impossible but rather unlikely to identify errors in a code review. Functional HDL simulation is the usual way to find it.

In several states, your state machine can only advance if the expected output is read from the controller. Respectively it's stuck if the result is different.

 

[wowpro7]

Generally I'd prefer a more hierarchical structure with SPI read/write performed in separate modules.

Not impossible but rather unlikely to identify errors in a code review. Functional HDL simulation is the usual way to find it.

In several states, your state machine can only advance if the expected output is read from the controller. Respectively it's stuck if the result is different.

can you give an example of separating read and write in SPI. i am working on doing things correct, not just work.

back to the question,
i have run simulation in Vivado and the code seems to do what intended, my guess the problem is in the way i configure the RFID module.
have you encountered with this module before?

This is impossible to read.

Please adjust your formatting. Lines like “end else begin” are just horrible. Use indentations (your editor should do it for you). The TAB key is your friend.

you are truly correct, thanks to the moderator it was fixed. please take a look again.

 

[ads-ee]

Using adders to transition states may not lead to very good synthesis results. I'm not sure if it will actually be recognized as an FSM.

You might also what to reconsider using cod that indexes into a vector to updated each bit. SPI is a serial protocol, so code a shift register it will run faster and use less logic overall.

 

[wowpro7]

Using adders to transition states may not lead to very good synthesis results. I'm not sure if it will actually be recognized as an FSM.

You might also what to reconsider using cod that indexes into a vector to updated each bit. SPI is a serial protocol, so code a shift register it will run faster and use less logic overall.

it does work and syntesised correctly. you are right that i am using allot of logic when i am counting and using a shift may seem better. but how do you shift MSB first? it will still require a counter.

back to the question,
have you encountered with MFRC522 ?