Program to FPGA communication on MAC layer

[Tajira]

Hi all,
I am working on Project where I will design an FPGA based data process accelerator. For that purpose I need to connect that FPGA (Xilinx V5 - evaluation board) to a PC with Ethernet port.
Now there few problems which needed to be addressed.
1) If I load full UDP/IP stack in FPGA then it occupies too much space, and there remains few space for my accelerator.
2) If I dont use UDP/IP then how will I communicate with a program(planning to write in Python) working on PC.

So, in nutshell, my question is that : is there any way that I only load MAC IP in FPGA and yet Frames formed by it are received by a program running on a PC? In that case how will be address a particular program?

Please note that I know Python and Verilog. Just need little guidance.

 

[dpaul]

So, in nutshell, my question is that : is there any way that I only load MAC IP in FPGA and yet Frames formed by it are received by a program running on a PC?

I think it is possible if data is Tx in the correct frame structure from FPGA to PC.
See your MAC IP core will definitely implement a MAC address. Now you have to let your PC know that an IP address exists for that MAC address.

How to do that?
You need to make an entry into the ARP table of your PC. So in the cmd prompt (admin mode) run this:
arp -s 192.168.1.13 DA-01-02-03-04-05

When I was ping testing the Xilinx TEMAC core it had the MAC address DA-01-02-03-04-05 to which I had assigned IP 192.168.1.13. I could ping the TEMAC core from my PC. In my case the MAC core was simply connected in a loopback mode on the FPGA. All packet communication can be tracked via Wireshark.

In your case if your logic inside the FPGA (which will include the MAC core) can create valid frames (a MAC creates valid frames, but you must supply it with the data to create valid frames), I don't see any reason why it can't be received by the Eth card of your PC after the address mappings have been done.

 

[ads-ee]

Hi all,
I am working on Project where I will design an FPGA based data process accelerator. For that purpose I need to connect that FPGA (Xilinx V5 - evaluation board) to a PC with Ethernet port.
Now there few problems which needed to be addressed.
1) If I load full UDP/IP stack in FPGA then it occupies too much space, and there remains few space for my accelerator.
2) If I dont use UDP/IP then how will I communicate with a program(planning to write in Python) working on PC.

So, in nutshell, my question is that : is there any way that I only load MAC IP in FPGA and yet Frames formed by it are received by a program running on a PC? In that case how will be address a particular program?

Please note that I know Python and Verilog. Just need little guidance.

I've implemented UDP in a number of FPGA designs and the MAC interface IP core plus UDP header parsing was never that large. I'm not sure what you are implementing but this seems like you may be using something with excess features that you don't need.

 

[Tajira]

I think it is possible if data is Tx in the correct frame structure from FPGA to PC.
See your MAC IP core will definitely implement a MAC address. Now you have to let your PC know that an IP address exists for that MAC address.

How to do that?
You need to make an entry into the ARP table of your PC. So in the cmd prompt (admin mode) run this:
arp -s 192.168.1.13 DA-01-02-03-04-05

When I was ping testing the Xilinx TEMAC core it had the MAC address DA-01-02-03-04-05 to which I had assigned IP 192.168.1.13. I could ping the TEMAC core from my PC. In my case the MAC core was simply connected in a loopback mode on the FPGA. All packet communication can be tracked via Wireshark.

In your case if your logic inside the FPGA (which will include the MAC core) can create valid frames (a MAC creates valid frames, but you must supply it with the data to create valid frames), I don't see any reason why it can't be received by the Eth card of your PC after the address mappings have been done.

nice.... I will get back to you with in few days. Thanks