afc89
Newbie level 1
Im trying to synthesize a processor in verilog.
In the design Register files are asynchronous read and forwarding is used.
If I use Synchronous read ,how to overcome stale data problem (like forwarding in earlier case) other than stalling ?
In the design Register files are asynchronous read and forwarding is used.
If I use Synchronous read ,how to overcome stale data problem (like forwarding in earlier case) other than stalling ?
