A lot of data converter topologies rely on matching (for capacitance, resistance, delay, etc.) - in such a case, PVT analysis won't give you much (everything is changed the same way, very often - artificially so).
A systematic, layout-based (i.e. parasitics) mismatch is much more important here.
Process corner simulations are to be done usually only if you are planning to hit very high yield, as you can clearly distinguish the process corner of each and every chip just post fabrication and throw away the non-typical ones outside some sigma variation.