Process (clock)
begin
if rising_edge (clock) then
b <= a;
c <= b;
end if;
end process;
The statements assigning signals INSIDE a process are NOT sequential.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 process(clk) begin if rising_edge(clk) then some_sig <= '0'; -- default if some_condition_occurs then some_sig <= '1'; end if; end if; end process;
All VHDL code is sequential
Simply put, if there is any FF inferred then it is a sequential logic, otherwise it would be combinational, isn't it ?
b <= a;
c <= b;
c <= b;
b <= a;
The statements assigning signals INSIDE a process are NOT sequential. (VARIABLES are a different story, but ignore them for now). If you drew a schematic of what the process actually represents it would make more sense. Think of it this way. There are 2 flip-flops, B and C.
The D input of B is A; the D input of C is the Q output of B. Thus, when the clock edge occurs both B and C are updated with the value of their D inputs PRIOR to the clock edge.
YOU MUST THINK OF THIS IN HARDWARE TERMS. THIS IS NOT SOFTWARE!!!!
As you'll see from my example, that cannot be the case, otherwise some_sig would have multiple drivers, as it is being driven to '0' and '1' in the same process, but it because of the fact that the code is sequential that it works.
Processes occur in parallel, but code within a process is sequential (from a simulation/execution pov). It may be synthesised into parallel circuits however.
Process (clock)
begin
if rising_edge (clock) then
b <= a;
c <= b;
end if;
end process;
I don´t like this "software"-like programming style.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 comb_proc : process(all) --because 2008 begin ns <= state; -- hold state op <= '0'; -- default state machine output case state is when state1 => --I did defaults so I didnt have to write explicit assignments in my 100 states, and get copy/pasta fails if some_condition then ns <= special_state; end if; when special_state => op <= 1; end case; end process;
If you look are respective clocks:
Time=0 a=1, b=2, c=3 (no clocks have occured yet)
Time=1 a=1, b=1, c=2 (first clock - this case holds until the next rising clock edge)
Time=2 a=1, b=1, c=1
right.
in this way, is the highlighted line the result of sequential execution?
it seems concurrent execution!
For simulation, a testbench might use a process with multiple wait statements -- this makes it much more clear that the process is evaluated in a sequence. Even if assignments eventually occur in parallel.
This is not how it works. If you've got a wait statement, then you can't have a clock. Signals will get assigned at the end of the wait time. Not at the end of the process.
This is not how it works. If you've got a wait statement, then you can't have a clock. Signals will get assigned at the end of the wait time. Not at the end of the process.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -- Infers a register in all synth tools process begin wait until rising_edge(clk); op <= ip; end process; -- should also synthesis and infer register process begin wait on clk; if rising_edge(clk) then op <= ip; end if; end process; --also infers a register op <= ip when rising_edge(clk);
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