problems with vhdl resize function

[gemma_g]

Hi guys, i am having a problem with the function and could really do with some help... probably best if i jsut show you the code to explain

so...(giving you everything here)...

-- signal declarations

type t_DDR2_MEMSPACE_CFG_REC is
record
start_address : std_logic_vector(g_DDR2_CTLR_ADDR_WIDTH-1 downto 0);
end_address : std_logic_vector(g_DDR2_CTLR_ADDR_WIDTH-1 downto 0);
end record;

type t_ARRAY_DDR2_MEMSPACE_CFG_REC is array(natural range <>) of t_DDR2_MEMSPACE_CFG_REC;

signal ddr2_memspace_cfg : t_ARRAY_DDR2_MEMSPACE_CFG_REC(st_CHANNELS_RANGE) := (others => c_DEFAULT_VAL_MEM_CFG);

-- i declare these signals inside a generate (for c in st_CHANNELS_RANGE)
signal wr_addr : unsigned(15 downto 0) := (others => '0');
wr_address_gt_memory_end : std_logic := '0';

throughout the rest of the code these are all good - i can read/write them, compile and simulate nae bother, but, when i try and do the following assignment Modelsim is not a happy chappy..

wr_address_gt_memory_end(c) <= '1' when std_logic_vector(resize(unsigned(wr_addr(c)), g_DDR2_CTLR_ADDR_WIDTH)) > ddr2_memspace_cfg(c).end_address) else '0';


--- errors
No feasible entries for subprogram "RESIZE".
Cannot resolve expression type of infix expression.
Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).
Type conversion (to ieee.std_logic_1164.STD_LOGIC_VECTOR) conflicts with expected type std.STANDARD.BOOLEAN.



i've had problems with resize before - usually brackets in the wrong place, that kind of thing but i am starting to pull my hair out over this one and am sure i am just making some kind of schoolboy error with it, just can't work out what.. grrrr

can anyone throw any light on it for me???? (have all the correct libs for resize and use it elsewhere in the code already)

cheers in advance,

gems

 

[FvM]

-- i declare these signals inside a generate (for c in st_CHANNELS_RANGE)
signal wr_addr : unsigned(15 downto 0) := (others => '0');
wr_address_gt_memory_end : std_logic := '0';

How? wr_addr would be expected to be defined as an array type in this case.

wr_addr(c) refers to a single bit with the shown signal declaration.

There are possibly more problems, but the said points should be clarified first.

 

[gemma_g]

Thank you, I posted in a xilinx forum and somebody else helped me out with the answer too - i knew it was something simple staring me in the face so thank you for putting a fresh set of eyes on it. i replaced the line with:

wr_address_gt_memory_end(c) <= '1' when std_logic_vector(resize(unsigned(wr_addr), g_DDR2_CTLR_ADDR_WIDTH)) > ddr2_memspace_cfg(c).end_address) else '0'; -- remove (c) from wr_addr as it is already in a generate statement.

really appreciated the help - saved my bacon.

gem