module Main(
// 6809 side
input [15:0] Addr, // Dragon address bus
inout [7:0] Data, // Daragon data bus
input E, // E clock
input Q, // Q clock
input RW, // Read/Write
input Reset, // System reset
);
reg [15:0] SAMBits; // 1 bit x 16 bit array.....
// Generate OE and WE signals, only do this if Reset is high !
assign RD = E & RW & Reset;
assign WR = E & ~RW & Reset;
assign SAMBitsAddr = ((Addr>=16'hFFC0) && (Addr<=16'hFFDF));
assign SAMBitsWR = SAMBitsAddr & WR;
always @(posedge SAMBitsAddr or negedge Reset)
begin
if (!Reset)
begin
case (Addr[5:1])
4'b0000 : SAMBits[0] <= Addr[0];
4'b0001 : SAMBits[1] <= Addr[0];
4'b0010 : SAMBits[2] <= Addr[0];
4'b0011 : SAMBits[3] <= Addr[0];
4'b0100 : SAMBits[4] <= Addr[0];
4'b0101 : SAMBits[5] <= Addr[0];
4'b0110 : SAMBits[6] <= Addr[0];
4'b0111 : SAMBits[7] <= Addr[0];
4'b1000 : SAMBits[8] <= Addr[0];
4'b1001 : SAMBits[9] <= Addr[0];
4'b1010 : SAMBits[10] <= Addr[0];
4'b1011 : SAMBits[11] <= Addr[0];
4'b1100 : SAMBits[12] <= Addr[0];
4'b1101 : SAMBits[13] <= Addr[0];
4'b1110 : SAMBits[14] <= Addr[0];
4'b1111 : SAMBits[15] <= Addr[0];
endcase
end
else
begin
SAMBits[15:0] <= 0;
end
end
assign SAMBitsH = (Addr==16'hFF58);
assign SAMBitsL = (Addr==16'hFF59);
assign SAMBitsRD = (SAMBitsL | SAMBitsH) & RD;
wire [7:0] SAMData;
assign SAMData = SAMBitsL ? { SAMBits[7], SAMBits[6], SAMBits[5], SAMBits[4], SAMBits[3], SAMBits[2], SAMBits[1], SAMBits[0]} :
{ SAMBits[15], SAMBits[14], SAMBits[13], SAMBits[12], SAMBits[11], SAMBits[10], SAMBits[9], SAMBits[8]};
// When the Dragon reads give it the AVR data / status
// Note both reading the AVR data reg & the PIA override give the AVRToDragon reg.
wire [7:0] DragonDataOut;
assign DragonDataOut[7:0] = SAMBitsRD ? SAMData :
AVRStatus ? {5'b0,AVRW_DragonR,DragonW_AVRR,AVRBusy} :
RamCTRLRD ? {MapMode,NMIEn,RAMVec,ROMA14, RomWE, FIRQEn, RamWP, RamEnable} :
AVRToDragon;
assign Data = (DragonIORD | AVRStatusRD | RamCTRLRD | SAMBitsRD | PIACS) ? DragonDataOut : 8'bz;
endmodule