I've got some problems passing Assura LVS to a symmetrical circuit. Assura tells me that I've to exchange the pins. If I do it, LVS is done succesfully, but I think it should pass even if I don't exchange them. I've also tried to pass Diva LVS and it has done it succesfully.
I also have other circuits that are based on the symmetrical one and they have passed Assura and Diva LVS succesfully.
Can anybody help me, please?
Thanks
I've got some problems passing Assura LVS to a symmetrical circuit. Assura tells me that I've to exchange the pins. If I do it, LVS is done succesfully, but I think it should pass even if I don't exchange them. I've also tried to pass Diva LVS and it has done it succesfully.
I also have other circuits that are based on the symmetrical one and they have passed Assura and Diva LVS succesfully.
Can anybody help me, please?
Thanks
I think assura has some sensitivity to the order of the pins. So if the order in which the layout netlist pins are if it does not match with the schematics then also you get errors.
Please take note that Assura is a pure hierarchical tool.
Your problem is most likely because you did not use the version suitable for the Process Design Kit.
You can simply put any Process Design Kit into any version of cadence and wack out the result. Things will turn out wrong.
Make sure the Cadence you use is of recommmended by your foundry.
One interesting you should note is that if you do noise simulation in IC446 and noise simulation in version IC5.0 Both gave you different results.
If you ask me, i will tell you that please use IC5.033. DO not use IC5.0 as it has pretty much problem.
I've already solved my problem. The thing was that I was using the symbol of the circuit as schematic. But it seems that Assura doesn't work well with symbol views. So I had to use the schematic view and put the pines there.
Thanks to everybody.