Problems with frequency hopping in PLL

[saulbit]

I am designing a CW source, and I have to make frequency hopping in frequency range of 1.5GHz~2.0GHz. The main chip is ADF4350, in which a PLL and a VCO is integrated. The PLL works well when it outputs a single frequency number, however, when it is used to hop, there is something spur in the spectrum analyzer. It seems to be the unlock spur during hopping process. The Mute-Till-Lock-Detect is enabled. I wonder can PLL used in frequency hopping, since when the frequency is changed, there must be unlocking time, so during the unlocking time, the VCO outputs may be spur. So how can I realize the frequency hopping process. Well, to be exact, the frequency sweeping process.

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Here is the datasheet of ADF4350. Thanks!

 

[tony_lth]

What is your purpose of freq hopping?
What is your requirements of hopping? How fast?
What is your requirements on spurs?
No purpose, no answer.

 

[saulbit]

What is your purpose of freq hopping?
What is your requirements of hopping? How fast?
What is your requirements on spurs?
No purpose, no answer.

Hi Tony. I am designing this source for frequency sweeping, something like FM, as a stimulation or a input for two-port network. It is not used in any defense programme, as you know, that PLL sweeping speed is too low for EW. The dwelling time from 800us to 1ms is needed. The locking time of the PLL is about 600us. The spur limitation is -70dBc. However, we can only achieve the spur to be -35dBc, which can not be used at all!

 

[jiripolivka]

Hi Tony. I am designing this source for frequency sweeping, something like FM, as a stimulation or a input for two-port network. It is not used in any defense programme, as you know, that PLL sweeping speed is too low for EW. The dwelling time from 800us to 1ms is needed. The locking time of the PLL is about 600us. The spur limitation is -70dBc. However, we can only achieve the spur to be -35dBc, which can not be used at all!

To my experience, most PLL oscillators need a certain lock time to engage. If you need to frequency hop, the best way would be to use several PLL ICs with desired frequency outputs, and switch them as needed.
For frequency sweep, the transition from one frequency to another can be adjusted so fast as the PLL system can lock and lock again.
During the lock process, spurs almost always appear, again a good idea to add a switch that opens after the lock is finished.

 

[FvM]

At best, the PLL will sweep linearly between both frequencies. Watching the sweep with a regular SA will possibly show some arbitrary lines inbetween, but hardly a continuous band.

Simple questions:
- can you tolerate the transient signal involved with a linear sweep, otherwise you need to disconnect the output in any case.
- if a linear sweep is O.K., are you sure about the actual behaviour? Is your measurement setup able to acquire it?
- did you check if the PLL loop bandwidth is suffcient to perform a sweep without losing lock?

 

[saulbit]

It is an agony program for me. The money payer don't know anything but the performance of Agilent signal sources. So they don't even listen to our explanation. That is the true fact.

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Perhaps we need an and gate for the pulse modulation switch. The inputs of the and gate is PLL Lock Detect Output and another is the pulse sources. It is the first time for me to do such a job. And that may be the way Agilent sources do.

 

[biff44]

two things that are always true in microwave engineering:

1) the "money payer" gets his way, lest he not pay you for your effort
2) NEVER say it cant be done, lest you be embarrassed by another engineer's novel idea

So, you do NOT want a cw source. How about, instead of trickling out your needs, you actually post your specification here: range, settling time, frequency step size if it EVER is actually in CW mode, Sweep time, spurious, phase noise, vibration, etc etc. Then we might be inclined to help you out

 

[BigBoss]

You may disconnect the VCO output during hopping period.
First you disconnect the VCO output, then you immediately start to lock the PLL after locking occurs you connect again the VCO output to SA/to other circuits..
Just an idea..