Problems with compiling files to different libraries in NC

[alpacinoliu]

I am a newbie to nc.
I want to compile modules in a file common.v into the lib common, and other modules are compiled into the lib worklib.
Now I created the following files
cds.lib
DEFINE worklib ../bin/lib/worklib
DEFINE common ../bin/lib/common

hdl.var
DEFINE WORK worklib
DEFINE LIB_MAP (../rtl/common.v =>common)

but I found all modules was compiled into lib worklib. Am I right? how I do to meet my requirements

Thanks in advance

 

[omara007]

Re: nc!

in the main menu of the NC .. go to File .. Set Design Directory .. and then change the name of the work library from worklib (which is the default) into (common) .. and point to the physical directory that u want it to be ur library directory ..

 

[pheobe]

Re: nc!

I'm confused by this problem now.

Have anybody resolve this problem in the hdl.var way?

thanks in advance!

 

[ljxpjpjljx]

Re: nc!

you can use ncsim to generate the cds.lib and hdl.var!

 

[pheobe]

Re: nc!

you can use ncsim to generate the cds.lib and hdl.var!

but i want to create cds.lib and hdl.var automatically with my csh script

 

[ljxpjpjljx]

Re: nc!

you can also prepare for your own cds.lib and hdl.var ,then tell ncsim to load this file !

 

[pheobe]

Re: nc!

i find the reason in nc help as following:

If the WORK variable (see WORK) and the LIB_MAP variable are both defined, the definition of the WORK variable overrides the definition of the LIB_MAP variable. This is important to remember if you are doing a mixed-language simulation, where you might define the LIB_MAP variable to control where the Verilog design units are compiled and then define the WORK variable to define the work library for SystemC. In this case, all design units would be compiled into the library specified with the WORK variable. To avoid this, you can either remove the definition of the WORK variable and then use the -work command-line option when compiling SystemC, or you can remove the definition of the LIB_MAP variable and then use the -work option when compiling Verilog.