Re: clock synthesization
Before answering u , i want to suggest you one thing. Whenever you are writing the code make sure that what hardware you are expecting for your code from the synthesis tool .
You said you want to change the state on both edges of the clock (I wonder ??) and ur code is
if (bup'event) then
state<= next_state
I think the above statement will never generate a flipflop (if synthesizable ??)instead it may generate a combinational circuit . You can't define a single flipflop which can output on both edges of the clock(I wonder if ?? and I want to see if any one provide ).
If you really want the output to be effected on both edges of the clock then use two seperate set of registers one operating with the pos edge of the clock and other with the neg edge of the same clock and assign the result of these two blocks concurrently to the final output.
I hope u got it ?? You try ur code as i said above and synthesize the code.
If I misunderstood ur problem plz let me know in detail about the same .
best regards,
subbu.